Hi,
this outputs your desired frequency:
Your FPGA just needs to read the VGA pins with this clock? I hope the VGA runs with the video pll?
Perhaps you need to adjust the divisors to match the ones of the VGA lib.
I hope you get it running - I spent some time to write this code for you ;-)
this outputs your desired frequency:
Code:
//(c) Frank B
//
// - Configures Video PLL to output 25.175MHz via I2S on PIN23 -
//
#define PADCONFIG ((0 << 0) | (4 << 3) | (0 << 6)) //Pg 622 Reference Manual
#define PLL_DENOMINATOR 960000 // MCUexpresso says 960000 max (thx DM5SG)
#define PLL_NOMINATOR 450000
#define PLL_DIV 1
#define PLL_DIV_SELECT 31 // this gives PLL = 755250000 Hz
#define PLL_POST_DIV_SELECT 2 // = 377625000 Hz
#define I2S_PRED 3 // = 125875000 Hz
#define I2S_PODF 5 // = 25175000 Hz
const uint8_t translate_pll_post_div[] = { 2, 1, 0, 0 };
const uint8_t translate_pll_video_div[] = { 0, 1, 0, 3 };
void setup() {
Serial.begin(9600);
//Setup PLL Divisiors:
CCM_ANALOG_PLL_VIDEO = CCM_ANALOG_PLL_VIDEO_BYPASS | CCM_ANALOG_PLL_VIDEO_ENABLE
| CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(translate_pll_post_div[PLL_POST_DIV_SELECT - 1]) // 0: 1/4; 1: 1/2; 2: 1/1
| CCM_ANALOG_PLL_VIDEO_DIV_SELECT(PLL_DIV_SELECT);
CCM_ANALOG_MISC2 = (CCM_ANALOG_MISC2 & ~(CCM_ANALOG_MISC2_VIDEO_DIV(3)))
| CCM_ANALOG_MISC2_VIDEO_DIV(translate_pll_video_div[PLL_DIV - 1]);
//Setup PLL:
CCM_ANALOG_PLL_VIDEO_NUM = PLL_NOMINATOR;
CCM_ANALOG_PLL_VIDEO_DENOM = PLL_DENOMINATOR;
CCM_ANALOG_PLL_VIDEO_CLR = CCM_ANALOG_PLL_VIDEO_POWERDOWN;//Switch PLL on
//Wait for PLL Lock:
while (!(CCM_ANALOG_PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK)) {;};
//Disable PLL Bypass:
CCM_ANALOG_PLL_VIDEO_CLR = CCM_ANALOG_PLL_VIDEO_BYPASS;//Disable Bypass
//Setup I2S:
CCM_CCGR5 |= CCM_CCGR5_SAI1(CCM_CCGR_ON);
CCM_CSCMR1 = (CCM_CSCMR1 & ~(CCM_CSCMR1_SAI1_CLK_SEL_MASK))
| CCM_CSCMR1_SAI1_CLK_SEL(1); // &0x03 // (0,1,2): PLL3PFD0, PLL5, PLL4
CCM_CS1CDR = (CCM_CS1CDR & ~(CCM_CS1CDR_SAI1_CLK_PRED_MASK | CCM_CS1CDR_SAI1_CLK_PODF_MASK))
| CCM_CS1CDR_SAI1_CLK_PRED(I2S_PRED - 1) // &0x07
| CCM_CS1CDR_SAI1_CLK_PODF(I2S_PODF - 1); // &0x3f
// Select MCLK:
IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 & ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK))
| (IOMUXC_GPR_GPR1_SAI1_MCLK_DIR | IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(0));
I2S1_TMR = 0;
I2S1_TCR2 = I2S_TCR2_MSEL(1);
//Setup Pin:
CORE_PIN23_CONFIG = 3;
CORE_PIN23_PADCONFIG = PADCONFIG;
}
void loop() {}Your FPGA just needs to read the VGA pins with this clock? I hope the VGA runs with the video pll?
Perhaps you need to adjust the divisors to match the ones of the VGA lib.
I hope you get it running - I spent some time to write this code for you ;-)
