SD.open()?

Yes, that's the typical wiring. ( In front of the glasses. ) I wanted people to see how the thing was wired. That's why I posted the pic.

Would you think that twisting the MOSI and MISO wires with ground wires help?
 
Yes, that's the typical wiring. ( In front of the glasses. ) I wanted people to see how the thing was wired. That's why I posted the pic.
I was commenting about the subassembly behind the glasses. The foreground wiring is still a mystery … four neat bundles but no clue as to their source or destination.

Would you think that twisting the MOSI and MISO wires with ground wires help?
It would reduce emissions and pickup, but I’d be a bit surprised if it made a huge difference, unless the PWM is in the same bundle. Series resistors really do make a difference, I know from experience with SPI displays.
 
Series resistors (at the source) really help reduce EMI. They do this by slowing down the very fast rise time of digital signals, and tend to also knock down any over (and under) shoot. Those very fast signal edges contain high frequencies which are either conducted or radiated everywhere. SPI has very fast edge rates. Maybe your PWM does as well. The series resistors snub the rise time to a slightly slower rate, which should help out with the original poster's problem. Give it a try and report back.

We used snubbers (series resistors) to pass EMI testing for regulatory compliance of automotive radars. It was my job to get them through EMI. The EMI testing was for world wide regulatory compliance. (Most countries have their own regulations.) Traveled to Beijing for testing. The State Radio Testing Facility was pretty impressive.
 
Series resistors (around 22 to 100 ohms often) damp reflections/ringing on fast logic and thus stop double-clocking which can cuase malfunctioning, particularly for clock signals - they are not doing a lot for EMI though. Think of this as like damping a mechanical resonance. For really fast signals matched termination is used which prevents resonance and reflections very effectively without any bandwidth limiting - however this is typically power hungry.

Many CMOS logic chips can produce 2 to 5ns rise/fall times, which if being used for a serial output at 115200 baud is complete overkill as rise/fall of 500ns would be completely adequate. Adding a small series resistor here doesn't really do anything as serial signals / UARTs are inherently immune to double-clocking, though you could use larger R values and have an explicit RC filter, such as 1k / 470pF in this case.

To reduce EMI significantly you typically filter with ferrites and capacitors to slow the edges down a whole lot more (think like adding mechanical mass to slow down movement). However if the signal has to be fast you can't do that so much (unless its a differential signal where you can add a common-mode choke to reduce common-mode EMI). Using lower voltage also reduces EMI (and power), such as LVDS signals, commonly used where high baud rates are a requirement (100's of Mbaud)

Many chips designed to drive digital busses have control over rise/fall times, or are available in slower versions for use with slower busses. For instance you can get RS485 drivers at a range of top speeds.

The typical networks for sending a digital signal from one board to another involve EMI filtering at the sending end, rail-clamping protection diodes and more EMI filtering at the receiving end. Differential signalling is preferrable if you can afford the extra connections, especially with twisted-pair cabling.

You can model the EMI filters in Spice to get a feel for their behaviour (rather than just guess). The tricky part is knowing which signals will be the most problematical, as this depends on many factors, cable length and type, baud rate, voltage, singleded/differential, current levels, spectrum of the signal...

However EMI is also a problem on the power supply wiring, and much bigger filters are needed to reduce this as there are significant currents involved. Again ferrites and capacitors are typically used.
 
Series resistors (around 22 to 100 ohms often) damp reflections/ringing on fast logic and thus stop double-clocking which can cuase malfunctioning, particularly for clock signals - they are not doing a lot for EMI though. Think of this as like damping a mechanical resonance. For really fast signals matched termination is used which prevents resonance and reflections very effectively without any bandwidth limiting - however this is typically power hungry.

Many CMOS logic chips can produce 2 to 5ns rise/fall times, which if being used for a serial output at 115200 baud is complete overkill as rise/fall of 500ns would be completely adequate. Adding a small series resistor here doesn't really do anything as serial signals / UARTs are inherently immune to double-clocking, though you could use larger R values and have an explicit RC filter, such as 1k / 470pF in this case.

To reduce EMI significantly you typically filter with ferrites and capacitors to slow the edges down a whole lot more (think like adding mechanical mass to slow down movement). However if the signal has to be fast you can't do that so much (unless its a differential signal where you can add a common-mode choke to reduce common-mode EMI). Using lower voltage also reduces EMI (and power), such as LVDS signals, commonly used where high baud rates are a requirement (100's of Mbaud)

Many chips designed to drive digital busses have control over rise/fall times, or are available in slower versions for use with slower busses. For instance you can get RS485 drivers at a range of top speeds.

The typical networks for sending a digital signal from one board to another involve EMI filtering at the sending end, rail-clamping protection diodes and more EMI filtering at the receiving end. Differential signalling is preferrable if you can afford the extra connections, especially with twisted-pair cabling.

You can model the EMI filters in Spice to get a feel for their behaviour (rather than just guess). The tricky part is knowing which signals will be the most problematical, as this depends on many factors, cable length and type, baud rate, voltage, singleded/differential, current levels, spectrum of the signal...

However EMI is also a problem on the power supply wiring, and much bigger filters are needed to reduce this as there are significant currents involved. Again ferrites and capacitors are typically used.
All true. However, series resistors have their place. They are cheap and relatively easy to patch into a circuit. And often they work well enough to get by. The original poster noted problems when their PWM signal was on. I've seen conducted EMI from SPI and fixed most of it using (fixed) resistors varying from 22 to 100 ohms.

The "right way" is to use an oscilloscope to view signals while running and determine if they look unusual. However, that means you have the experience to know what normal looks like.

Slaying the EMI demon can be quite difficult, even for professionals. Especially since the issue shows up towards the end of the design cycle, when no one wants to spend money anymore, nor delay production.

Often, it may not be EMI at all. Sadly, it simply can be software, or sequencing that's the issue. An scope or clever time stamping can help identify if things are running correctly. But a time stamp can't show you if you have serious overshoot and double clocking. SPI is susceptible to this on the clock and control lines, unlike a uart which has some protection built in.
 
Well, for now, I'm just dropping the fancy fade ins and outs. I can at least move forward on the rest of the codebase. Come this fall, when my EE get's back, we can take out the scope and have a look at what's actually going on. Maybe come up with a positive fix.
 
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