Hi all. A while back I was working on an audio-reactive LED project. Because of the physical location, the most convenient way to bring the audio to the Teensy was via an optical SPDIF connection. I started working with the TI DIR9001 mostly because it’s available on a preassembled eval board containing all required components for Optical SPDIF --> I2S conversion. You just connect power, the optical input, and the I2S signals. I posted the resulting code in this forum
The main drawbacks of the DIR9001 are that it’s unidirectional only (it can’t do I2S --> SPDIF) and the eval board is ridiculously expensive.
Then I ran across the WM8804 from Cirrus Logic. This device solves both of the above problems as it is bidirectional and there is a very reasonably-priced board available.
So, I created several new classes based on the Quad I2S classes in the Audio Library. The major changes are accommodating a BCLK frequency of 64 * Fs and support for Teensy to operate in I2S Slave mode. The library code and two examples are attached. The connections supporting the examples are:

As when using dual Audio Adaptor Boards, you need to disconnect Teensy Pin 15 from Audio Adaptor Pin 15. Otherwise, the bypass cap on the later kills the high frequency IS0_TXD1 signal. I cut the pin, you can probably also just remove the cap.
When a SPDIF input is present, the WM8804 must act as I2S master to synch up MCLK, BCLK, and LRCLK with this input. In this case, the I2S interfaces in the Teensy are set for Slave mode and all Audio object timing is frequency synchronous with the WM8804. The 'Quad_I2S_SlaveExample' example blends audio from 2 independent sources -- SPDIF / WM8804 and the SGTL5000's ADC on the Audio Adaptor. It then outputs the resulting signal to 3 destinations -- back to the WM8804 board for I2S --> SPDIF Out conversion, to the DAC on the SGTL5000, and to Teensy's onboard DAC. The pot sets the blending level between the two sources. The connections from the Audio Design tool look like this:

When there is no SPDIF input but SPDIF output is desired, then the WM8804 is set for Slave mode and Teensy becomes the I2S master. All Audio object timing is now derived from Teensy's clock. The 'Quad_I2S_MasterExample' accepts I2S audio input from the SGTL5000 and outputs it to the same 3 destinations as above. The connections from the Audio Design tool look like this:

The only real drawback of this WM8804 board is the documentation -- there isn't any. Well, there is a short User Manual, but it's written in Chinglish and is essentially useless. The company won't release the schematic either which would be helpful in figuring out the switch settings. But after a little head scratching I worked it out. The WM8804 datasheet is pretty good.
Anyway, I hope someone finds this useful.
PS -- There is a short description of each new class in the respective .h files -- just under the PJRC copyright notice.
The main drawbacks of the DIR9001 are that it’s unidirectional only (it can’t do I2S --> SPDIF) and the eval board is ridiculously expensive.
Then I ran across the WM8804 from Cirrus Logic. This device solves both of the above problems as it is bidirectional and there is a very reasonably-priced board available.
So, I created several new classes based on the Quad I2S classes in the Audio Library. The major changes are accommodating a BCLK frequency of 64 * Fs and support for Teensy to operate in I2S Slave mode. The library code and two examples are attached. The connections supporting the examples are:

As when using dual Audio Adaptor Boards, you need to disconnect Teensy Pin 15 from Audio Adaptor Pin 15. Otherwise, the bypass cap on the later kills the high frequency IS0_TXD1 signal. I cut the pin, you can probably also just remove the cap.
When a SPDIF input is present, the WM8804 must act as I2S master to synch up MCLK, BCLK, and LRCLK with this input. In this case, the I2S interfaces in the Teensy are set for Slave mode and all Audio object timing is frequency synchronous with the WM8804. The 'Quad_I2S_SlaveExample' example blends audio from 2 independent sources -- SPDIF / WM8804 and the SGTL5000's ADC on the Audio Adaptor. It then outputs the resulting signal to 3 destinations -- back to the WM8804 board for I2S --> SPDIF Out conversion, to the DAC on the SGTL5000, and to Teensy's onboard DAC. The pot sets the blending level between the two sources. The connections from the Audio Design tool look like this:

When there is no SPDIF input but SPDIF output is desired, then the WM8804 is set for Slave mode and Teensy becomes the I2S master. All Audio object timing is now derived from Teensy's clock. The 'Quad_I2S_MasterExample' accepts I2S audio input from the SGTL5000 and outputs it to the same 3 destinations as above. The connections from the Audio Design tool look like this:

The only real drawback of this WM8804 board is the documentation -- there isn't any. Well, there is a short User Manual, but it's written in Chinglish and is essentially useless. The company won't release the schematic either which would be helpful in figuring out the switch settings. But after a little head scratching I worked it out. The WM8804 datasheet is pretty good.
Anyway, I hope someone finds this useful.
PS -- There is a short description of each new class in the respective .h files -- just under the PJRC copyright notice.