SPI Slave for T4, DMA SPI Slave

[sicco]

There was https://forum.pjrc.com/threads/72792-Teensy-4-1-SPI-Slave-here-it-is but it did not do the job properly for me. I wanted to sniff another SPI bus in another system, and blocking code does not let me do that.

So I went DMA again.

Attached an example that does SPI sniffing. It uses two T4 SPI hardware ports. One looks at the to be monitored MOSI line, the other looks at the to be monitored MISO line. In my case it was about sniffing what goes on in the insides of a Tektronix TDS3000 scope.

The T4_DMA_SPI_SLAVE .h and .cpp offers the three iMXRT SPI ports that are externally wireable on Teensy41.
Alternative pins can be used.
SDI and SDO pin functions can be swapped.

Inputs when used have pullups and Schmitt triggers enabled.



Output looks like this:

C:\Users\HP\OneDrive\Documents\Arduino\T4_DMA_SPI_SLAVE_Example\T4_DMA_SPI_SLAVE_Example.ino Aug 24 2023 18:03:47
T4_DMA_SPI_SLAVE Example - 4 wire SPI bus MODE0 Sniffer
Teensy41 uses two SPI ports to sniff traffic on another SPI port between a SPI master and an SPI slave (that are not part of this Teensy).
Teensy41 SPI port sniffs the to-be-sniffed_bus MOSI line.
Teensy41 SPI1 port sniffs the to-be-sniffed_bus MISO line.
Both Teensy41 SPI and SPI1 ports must have their CS and SCK pins hardwired together and wired to the to-be-sniffed_bus /CS and SCK lines.
Both Teensy41 SPI and SPI1 ports are in SLAVE mode.
T4_DMA_SPI_SLAVE port has SCK on INPUT pin 13, SDIN on pin 12 is RX, CS on INPUT pin 10
T4_DMA_SPI_SLAVE1 port has SCK on INPUT pin 27, SDIN on pin 1 is RX, CS on INPUT pin 0
begin done

n=0, [>4,<4] >0b <0b >00 <00 >00 <00 >0a <0a 5 us traffic for 4 bytes, est. f_SCK = 6.40 MHz, 7718.941 ms inter_trxn
n=1, [>4,<4] >0b <0b >00 <00 >00 <00 >00 <00 5 us traffic for 4 bytes, est. f_SCK = 6.40 MHz, 6.000 ms inter_trxn
n=2, [>4,<4] >0b <0b >00 <00 >00 <00 >80 <80 5 us traffic for 4 bytes, est. f_SCK = 6.40 MHz, 2.105 ms inter_trxn
n=3, [>4,<4] >0b <0b >00 <00 >00 <00 >0b <0b 5 us traffic for 4 bytes, est. f_SCK = 6.40 MHz, 1386.555 ms inter_trxn
n=4, [>4,<4] >0b <0b >00 <00 >00 <00 >00 <00 5 us traffic for 4 bytes, est. f_SCK = 6.40 MHz, 5.960 ms inter_trxn
n=5, [>4,<4] >0b <0b >00 <00 >00 <00 >80 <80 5 us traffic for 4 bytes, est. f_SCK = 6.40 MHz, 2.098 ms inter_trxn
n=6, [>4,<4] >25 <25 >8f <8f >d6 <d6 >74 <74 5 us traffic for 4 bytes, est. f_SCK = 6.40 MHz, 2185.108 ms inter_trxn
n=7, [>4,<4] >25 <25 >8f <8f >d6 <d6 >6d <6d 5 us traffic for 4 bytes, est. f_SCK = 6.40 MHz, 100.274 ms inter_trxn
n=8, [>4,<4] >25 <25 >8f <8f >d6 <d6 >67 <67 4 us traffic for 4 bytes, est. f_SCK = 8.00 MHz, 101.098 ms inter_trxn
n=9, [>4,<4] >25 <25 >8f <8f >d6 <d6 >61 <61 5 us traffic for 4 bytes, est. f_SCK = 6.40 MHz, 199.994 ms inter_trxn
n=10, [>4,<4] >25 <25 >8f <8f >d6 <d6 >5b <5b 5 us traffic for 4 bytes, est. f_SCK = 6.40 MHz, 99.451 ms inter_trxn
n=11, [>4,<4] >25 <25 >8f <8f >d6 <d6 >56 <56 5 us traffic for 4 bytes, est. f_SCK = 6.40 MHz, 101.153 ms inter_trxn
n=12, [>4,<4] >25 <25 >8f <8f >d6 <d6 >52 <52 5 us traffic for 4 bytes, est. f_SCK = 6.40 MHz, 110.741 ms inter_trxn
n=13, [>4,<4] >25 <25 >8f <8f >d6 <d6 >4c <4c 5 us traffic for 4 bytes, est. f_SCK = 6.40 MHz, 87.990 ms inter_trxn
n=14, [>4,<4] >25 <25 >8f <8f >d6 <d6 >4e <4e 4 us traffic for 4 bytes, est. f_SCK = 8.00 MHz, 297.491 ms inter_trxn
n=15, [>4,<4] >25 <25 >8f <8f >d6 <d6 >50 <50 4 us traffic for 4 bytes, est. f_SCK = 8.00 MHz, 99.415 ms inter_trxn
n=16, [>4,<4] >25 <25 >8f <8f >d6 <d6 >54 <54 5 us traffic for 4 bytes, est. f_SCK = 6.40 MHz, 100.336 ms inter_trxn
n=17, [>4,<4] >25 <25 >8f <8f >d6 <d6 >5b <5b 5 us traffic for 4 bytes, est. f_SCK = 6.40 MHz, 99.982 ms inter_trxn
n=18, [>4,<4] >25 <25 >8f <8f >d6 <d6 >61 <61 5 us traffic for 4 bytes, est. f_SCK = 6.40 MHz, 100.045 ms inter_trxn
n=19, [>4,<4] >25 <25 >8f <8f >d6 <d6 >65 <65 5 us traffic for 4 bytes, est. f_SCK = 6.40 MHz, 102.375 ms inter_trxn
n=20, [>4,<4] >25 <25 >8f <8f >d6 <d6 >6b <6b 4 us traffic for 4 bytes, est. f_SCK = 8.00 MHz, 98.450 ms inter_trxn
n=21, [>4,<4] >25 <25 >8f <8f >d6 <d6 >69 <69 5 us traffic for 4 bytes, est. f_SCK = 6.40 MHz, 200.675 ms inter_trxn

 

[Rezo]

Can this be used without the CS pin?
I have a 3 wire serial device I want to sniff; It has serial data in, serial data out, serial clock, a Reset line and a Busy line (uPD780204 8 bit microprocessor)

 

[sicco]

Not really. Without CS pin, there is no way to detect the start and end of a N byte transaction. So then we cannot really tell what N is.
You could try manually pulsing what is the CS pin on the Teensy side, and then look at what it displays. If the traffic is sporadic then you might be able to get an idea what the bytes are going both ways, but it will be tough to make sense of it all.

 

[Rezo]

If I know I have 12 bytes and then a pause of 2ms between transfers, or perhaps a busy pin from the slave that will toggle high just before it starts to transfer, and low right after it ends - would I be able to make use of it?
The KEY1 signal seems to be acting as a busy/free indicator to the host device as to when it can send a message (DISPLAY IN), and during the time it receives a message, it also outputs one as well (DISPLAY OUT)
This is an old control board from a Pioneer CDJ1000 MK1 using a uPD780204 8 bit microprocessor

 

[sicco]

Maybe you could try to fake a CS signal, for example with a one-shot 1 ms timer, triggered by an edge on your SPI CLK signal?
I think all it needs is a CS rising edge as the indication that whatever happened before the rising edge is now a finished transaction.
In other words, with CS low, it will record all the bytes it sees on MISO and MOSI, until the rising edge of the SPI /CS signal. After that rising edge it shows you what was collected in the DMA buffers.

 

[Rezo]

I was thinking of maybe setting up some FlexIO timers an buffers to generate the clock as well as capture/send the data and DMA it into a buffer for the final implementation.

But I will have a go first with the SPI Slave example you posted above