TDM output with out of phase MCLK

aszasza

Member
Hi guys, I have a very annoying problem caused by a hardware bug in the TAS6424 (not E version) quad channel amplifier.
The problem is kinda explained here and here.
The solution requires MCLK to be out of phase with BCLK. I'm not very good with the deep stuff of the audio library, so my question is, can you please direct me a little? Is it even possible to change this is the SAI hardware?

Using I2S works fine on the chip but I already have the PCB's made(many of them) because I was assuming that the ti chip will behave according to its datasheet specs...
Thank you!
 
Why not delay the one of the clocks with hardware? MCLK is fast so even a small delay ought to do the job, two inverters in cascade with RC filter between is the old-school way. Or with a single 74HC14 you can delay by 2, 4, or 6 inverter stages...
 
That is is one way of solving the problem for sure and I have thought about it but I rather would like to have it fixed in software if possible. This is my question, is this even possible? If so, what should I do? The SAI hardware is quite complicated and there are a lot of experts here...
 
Would simpling inverting MCLK be a workable approach? That might well be supported in the SAI hardware (haven't checked though).
 
It is possible to invert it, tried it but unfortunately not helping. There must be a critical race condition so it actually need a delayed clock, probably a quarter period time would be good, thats like 10nS...
 
Just for reference, using the 74hc14 does work. I'm only using the BCLK though, it goes directly from the Teensy to the amp and the amp's MCLK is the same BCLK output from the Teensy just trough a few stages of the inverter. The amp does not like 512*fs for MCLK for whatever reason even though its in the datasheet.
I also had a look in the processors reference manual, I don't think its possible to use out of phase MCLK output. It would be nice if someone could prove me wrong.
 
Back
Top