Teensy 3.6 256MHz

[PaulStoffregen]

I posted a quick shout-out on Twitter, linking to this thread.

https://twitter.com/PaulStoffregen/status/1053666670760288257

 

[Frank B]

I posted a quick shout-out on Twitter, linking to this thread.

https://twitter.com/PaulStoffregen/status/1053666670760288257

View attachment 14989

Wow... Good opportunity for a poll. As far as I know so far, it works on every Teensy 3.6 I know of. But are there some that may not run 256MHz sucessfully?

 

[defragster]

I have 4+1 out on my desk - all connect and upload and work the same for Dhrystone.
<edit>: Forgot the acrylic beta unit that works as well ( that uses the different pinned MCU - and olde USB connector )

Compiled 'Fastest, pure-code, LTO' they do "int n = 111711;" iterations in 100,000 microseconds but use cycle counts between 25600053 and 25600188 for "Dhrystones per Second: 1117110.0"
{ 2 sometimes take 100,001 us and the cycle count isn't always the same - new high is 25600269 }

They also run it Smallest code with LTO - more like :: Micros Run Time: 212208 ... CycleCount Run Time: 54325295 ... Dhrystones per Second: 526938.687500000000

 

[manitou]

Wow... Good opportunity for a poll. As far as I know so far, it works on every Teensy 3.6 I know of. But are there some that may not run 256MHz sucessfully?

All 3 of my T3.6 seem to work at 256mhz (including early acrylic beta unit). Running linpack 250x250 float with Fastest, getting 49.4 mflops.

 

[TFTLCDCyg]

Wow!

With SPI-TFT´s like the FT81X works very stable!

TFT: NHD 5" FT813

Gameduino 2/3 library modified in order to get access directly to the SDIO reader of the teensy 3.6

Another test in order to verify the stability of the SDIO reader@256MHz

 

[XFer]

At the new 256 MHz core clock, what about the various bus speeds (RAM etc.)? Standard or overclocked as well?

 

[Frank B]

See Post #1
RAM is full speed 256MHz. USB is clocked by the 48MHz source (same as with 216MHz)

 

[Frassil]

Nice work!
Just did some testing with Audio library at 256 mhz and the Audio shield. Seems to work nicely!
I did need to edit some files for it to compile.

For output i2s F_CPU i did use:
#elif F_CPU == 256000000
#define MCLK_MULT 9
#define MCLK_DIV 204
#define MCLK_SRC 0

And for other outputs i did just enter some "random", so i could compile (dont use other output objects, so can't try)

 

[Frank B]

Nice work!
Just did some testing with Audio library at 256 mhz and the Audio shield. Seems to work nicely!
I did need to edit some files for it to compile.

For output i2s F_CPU i did use:
#elif F_CPU == 256000000
#define MCLK_MULT 9
#define MCLK_DIV 204
#define MCLK_SRC 0

And for other outputs i did just enter some "random", so i could compile (dont use other output objects, so can't try)

That's pretty amazing. Are you sure? How did you test it?
We always had problems with I2S >200MHz

 

[Theremingenieur]

I think that one important point is not using the PLL clock but the BUS clock with #define MCLK_SRC 0. That means that you have a lower frequency fed into the fractional divider which reduces potential overclocking problems.

 

[Frank B]

Ok, if this works, i'll make a pullrequest to make the AudioLibrary work.

 

[Frassil]

Only tested with my ears
180 and 192 mhz high pitch wave sounds good,
216 is horror,
240 got some random cracks and pops,
256 mhz with my settings above works nicely (with my ears)

Unfortunatly i only have a scope from 1960s that doesnt work so well.

Have only done small testing with my synth project, and so far so good

 

[Frank B]

I've added some pullrequests for SD.h and Wire.

With I2S, I had no luck so far - tested with PT8211

 

[Frassil]

But now i did step on another problem, that is totally out of reach with my skills.
As i said earlier, audio library did work nice at 256 mhz for me with audioshield, UNTIL i get above about 60% CPU usage by audio library interupts. Then i get total freeze.
With 192Mhz it's stable and nice when i max it out at about 90% usage.

 

[Frank B]

Hm, I'm currently working with the audio library (without I2S, but high CPU load), and I have no problems.
Your MCLK settings do not work for me.

@Paul: The audio library still needs some updates, and I want to do it. What shall we do with the clock settings? Use Dummys ? Show errors? Use Frassil's values?

 

[Theremingenieur]

I'd strongly suggest rewriting the I2S clock generation part of the objects in the audio library, always using F_BUS as the clock source and the clocks MCLK=256*FS, BCLK=64*FS can be generated according to the other audio objects which use the PDB to generate the frame clock from the same F_BUS to prevent stuttering and incoherencies between the objects.

 

[Frank B]

Hm, I'm currently working with the audio library (without I2S, but high CPU load), and I have no problems.
Your MCLK settings do not work for me.

@Paul: The audio library still needs some updates, and I want to do it. What shall we do with the clock settings? Use Dummys ? Show errors? Use Frassil's values?

@Paul, (I hope you're reading this) - Can you just say what you think is best? - I can add it to the audio-lib, then, so it will - at least - compile and will be usable for the dacs/adcs.
You don't need to invest time - I need your decision only