Teensy 4.1 and 512Mbit PSRAM

A

auron

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I am trying to find out if a pet project of mine would be doable with Teensy 4.1, but I need to sample and store about 240Mbit in one second - 2 channels, 12 bit, one second at 10 Mhz. (using separate ADCs like AD9230), optionally double that.

I only need one second, but I need to store it real-time. Pulling I can use slower USB no problem, and I do not want to use flash, because of the wearout.

Is there any hardware limitation I'm missing why Teensy 4.1 would not work with a chip like this?
www.infineon.com

S80KS5123GABHA020 - PSRAM (Pseudostatic RAM) | Infineon Technologies

S80KS5123GABHA020 is a 512 Mb HYPERRAM™ with 1.8 V, Octal xSPI interface, and 400 MBps throughput. Find data sheet, parameters and ordering information.
www.infineon.com www.infineon.com

I understand the window currently mapped to PSRAM is "only" 16 MB, but that could be changed in software, right?
 
Sorry, completely missed the form factor. Don't know where my head was.
Thanks for setting me straight.

Doing my research again, it seems 8MB/64Mbit per chip is the best we can get at the moment for SOP-8 PSRAM.

So I'll have to redesign and process the data on the Teensy. Or maybe try to stream the 240Mbit via USB. If I read that thread right, it might be doable.
 
jmarsh said:
How would you even get the data into the Teensy at that speed...
Click to expand...
Hm, there is loads of IO for parallel reads from the ADCs, and 10Mhz sampling rate seemed fair at 600Mhz chip clock.
Sure, I would likely need DMA, or maybe I could get by with well written ISR. But that has been done, I figured.
Why do you think that would be a problem?
 
The current 8MB PSRAM with 2 installed can work OK with the QSPI bus cranked up to 166.2MHz.

There are 16MB PSRAM chips becoming available soon for a total of 32MB/256Mb, but they are limited to about 120MHz with 2 on the QSPI bus for a theoretical 480Mb/sec. Don't know what the realistic maximum throughput would be with overhead though.
 
auron said:
Hm, there is loads of IO for parallel reads from the ADCs, and 10Mhz sampling rate seemed fair at 600Mhz chip clock.
Sure, I would likely need DMA, or maybe I could get by with well written ISR. But that has been done, I figured.
Why do you think that would be a problem?
Click to expand...
Because I know USB on the Teensy is the fastest serial interface and it maxes out at roughly 30MB/s. So that's borderline which really only leaves a parallel method, which in turn pretty much means using FlexIO but the number of consecutive pins available for use on a T4.1 is very limited...
 
At 240Mb/s, no breadboard prototype would work. Even the prototype should be done on a real pcb.

There are some FPGA eval boards fitted with SDRAM. Connect the ADC on one side, and fill the SDRAM with the fast data. It will ensure you keep the exact acquisition rate. And connect the Teensy on the other side with SPI, QSPI or FlexIO, to control and read the data at lower speed.
 
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