Will there be pads for extra io’s on the back for surface mount connectors like in the 4.0?
No, not like 4.0 or 3.2, 3.5 or 3.6. The only bottom side pads on Teensy 4.1 are for adding QSPI memory chips. If you don't add those chips, you can get access to 7 signals on those pads. But they're not at a spacing for a J-lead header like the pads on other boards. Accessing those pads is difficult. They're really meant for adding SOIC8 or (maybe) DFN8 package memory chips.
The PCB is 6 layers, the same as Teensy 4.0, but it brings out 8 more signals for I/O pins, 7 more signals for QSPI, 14 extra signals to control the Ethernet PHY chip, and 1 to control the USB host power. That's 30 more wires escaping the BGA area. The PCB is completely filled with routing on all 4 non-plane layers, and even a few signals escape along the edges of the ground plane layer. It just wasn't possible to escape any more signals to the right hand side of the PCB. More may have been possible towards the left side, but that area was committed to USB host and Ethernet, and power input & bootloader, so I just couldn't put a set of pads on the bottom side and keep ethernet and usb host to using convenient & durable through-hole pads.
I did briefly consider a HDI PCB, like Arduino is using for Portenta H7. But that's much more expensive! Currently 6 layers and 5 mil spacing and through vias is the "sweet spot" for maximizing a PCB before the cost goes up dramatically.
@Paul, you can change the max upload size in php.ini
Messing with the website config is absolute last thing I would do at a time when we're about to release new hardware and wrap up a major software release! I'm not an "IT guy", and right now Robin & I are struggling to run PJRC without employees due to Oregon's covid-19 shelter in place order. I need to prioritize what we do.