EXTMEM Memory Test, 8 Mbyte
CCM_CBCMR=B5AE8304 (88.0 MHz)
testing with fixed pattern 5A698421
testing with pseudo-random sequence, seed=2976674124
...
testing with fixed pattern 00000000
test ran for 36.43 seconds
All memory tests passed :-)
...
Memory Usage on Teensy 4.1:
FLASH: code:36796, data:6040, headers:8360 free for files:8075268
RAM1: variables:6944, code:34176, padding:31360 free for local variables:451808
RAM2: variables:12384 free for malloc/new:511904
...
memory Usage on Teensy 4.1:
FLASH: code:28100, data:7064, headers:8864 free for files:8082436
RAM1: variables:7680, code:25432, padding:7336 free for local variables:483840
RAM2: variables:12384 free for malloc/new:511904
Cool thanks is this what it meant to say? sorry for thew noob questions.
i cant get it to test the memory but
Yep I have a ext memory test 0mbyte better check something
Wow yes mate that worked all memory test passed. To much flux . Thanks ����
Starting with a T_4.1 and PSRAM soldered - Cool. github.com/PaulStoffregen/teensy41_psram_memtest
Then A copy of the Arduino IDE needs to be installed 1.8.x or 2.x.
Then Current TeensyDuino 1.57 for the IDE 1.8.x, or Teensy in IDE 2.x Board Manager after installing the PJRC URL to the Preferences Additional board mgr URL section:
https://www.pjrc.com/teensy/package_teensy_index.json
Then selecting the T_4.1 board in the IDE should build and work properly.
If Errors the Verbose console output might explain what went wrong.
<edit>
Downloaded and tested here to work with IDE 2.0.3 and TD 1.58 beta 3 ( 0.58.3 ) on T_4.1 w/8MB PSRAM:
Code:EXTMEM Memory Test, 8 Mbyte CCM_CBCMR=B5AE8304 (88.0 MHz) testing with fixed pattern 5A698421 testing with pseudo-random sequence, seed=2976674124 ... testing with fixed pattern 00000000 test ran for 36.43 seconds All memory tests passed :-)
build notes:
Code:... Memory Usage on Teensy 4.1: FLASH: code:36796, data:6040, headers:8360 free for files:8075268 RAM1: variables:6944, code:34176, padding:31360 free for local variables:451808 RAM2: variables:12384 free for malloc/new:511904 ...
Would be interesting if the method of clock speed change details were included and any test sketch that showed the FAIL issue.Hey, i want to mention that PSRAM memtest provided is not completely trustful and may say "all is fine" while it is really not It costed me a couple of hours until i figured it out btw. I'm working on a hobby project which will read/write the data to some 5v TTL bus (LVC4245a translators were used for level shifting). I was wondering ...
The speed is limited for a reason since it hasn't been proven/tested good above the current default speed where that PJRC test was meant to run.
I think it would be good to extend PSRAM testing sketch to cover this use as well, so those errors are caught by the test itself
Actualy there is a 16Kb rom in uint8_t array which i initially used (source generated with Python from actual file) to check if signals are ok, an it is located in the fastest (tight coupled) memory. Then as a next step i added EXTMEM array, and copied data over to it (with a very bold approach ofCould you share the specific test code you believe should be incorporated into the PSRAM test? Your description "just made a copy of the same data in regular memory, and was comparing read data from both arrays on the fly" leaves a lot of imagination. A much more specific proposal would be needed to consider adding another test to the published code.
dst[i] = src[i]
loop) and then in the main loop added WAIT signaling to mitigate possible delays (without it data was arriving too late on bus). And it was working very bad, i almost pulled my hair out as i do not have oscilloscope or data logic analyzer (yet) figuring out what's wrong with my WAITs...@@ -366,7 +359,7 @@ FLASHMEM void configure_external_ram()
// turn on clock (TODO: increase clock speed later, slow & cautious for first release)
CCM_CBCMR = (CCM_CBCMR & ~(CCM_CBCMR_FLEXSPI2_PODF_MASK | CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK))
- | CCM_CBCMR_FLEXSPI2_PODF(5) | CCM_CBCMR_FLEXSPI2_CLK_SEL(3); // 88 MHz
+ | CCM_CBCMR_FLEXSPI2_PODF(5) | CCM_CBCMR_FLEXSPI2_CLK_SEL(2); // 110.77 MHz
CCM_CCGR7 |= CCM_CCGR7_FLEXSPI2(CCM_CCGR_ON);
FLEXSPI2_MCR0 |= FLEXSPI_MCR0_MDIS;
That 'fail on write' is actually what I was looking at last on the SDRAM test evolution across speed changes.BTW, i'm gonna make a short sketch which reproduces the issue without any irrelevant code and will post it here. Actually, at the moment i'm not completely sure those were read errors. It might happen that those were write errors on copying data look (huh?). But i have no idea how to distinguish. So i'll just try to reproduce