KurtE
Senior Member+
Often times when I am playing around with a Teensy 4.1 that has PSRAM and I wish to use it, I find that the default 88mhz speed is too slow.
I am playing around right now with a T4.1 with an NT35510 display on it that is setup using a 16 data pin parallel interface, using 24 bit color, as such
I allocated a frame buffer in PSRAM 800*480*4 = 1536000, which needless to say it won't fit in DTCM nor DMAMMEM
When I try to do an update screen, to the display with FlexIO speed of about 30mhz,
the display does not update properly. Note: it also does not update properly using 16 bit colors, but does if configured for 120mhz...
Note: the 24 bit color mode also has issues at 120mhz PSRAM speed.
Originally, we started off at 88Mhz and there was a TODO to speed it up, as you can see in the blame listing, that was 4 years ago:
My assumption is that if we have not changed the default in 4 years, we probably wont.
In the past (and with my current sources I have this edited) like:
Which allows me to try things out, but this is a global change and as maybe not all PSRAMs are created equal,
and likewise I assuming that this same setting is used for QSPI Flash chips as well.
So, I was wondering if we should add an Api to core, that allows us to change it on a per sketch basis.
I currently experimenting in one of my sketches with a function that currently looks like:
Probably overkill, but wondering if something like this should be added to cores...
Kurt
I am playing around right now with a T4.1 with an NT35510 display on it that is setup using a 16 data pin parallel interface, using 24 bit color, as such
I allocated a frame buffer in PSRAM 800*480*4 = 1536000, which needless to say it won't fit in DTCM nor DMAMMEM
When I try to do an update screen, to the display with FlexIO speed of about 30mhz,
the display does not update properly. Note: it also does not update properly using 16 bit colors, but does if configured for 120mhz...
Note: the 24 bit color mode also has issues at 120mhz PSRAM speed.
Originally, we started off at 88Mhz and there was a TODO to speed it up, as you can see in the blame listing, that was 4 years ago:
My assumption is that if we have not changed the default in 4 years, we probably wont.
In the past (and with my current sources I have this edited) like:
Code:
// turn on clock (TODO: increase clock speed later, slow & cautious for first release)
//CCM_CBCMR = (CCM_CBCMR & ~(CCM_CBCMR_FLEXSPI2_PODF_MASK | CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK))
// | CCM_CBCMR_FLEXSPI2_PODF(5) | CCM_CBCMR_FLEXSPI2_CLK_SEL(3); // 88 MHz
CCM_CBCMR = (CCM_CBCMR & ~(CCM_CBCMR_FLEXSPI2_PODF_MASK | CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK))
| CCM_CBCMR_FLEXSPI2_PODF(5) | CCM_CBCMR_FLEXSPI2_CLK_SEL(1); // 120?
CCM_CCGR7 |= CCM_CCGR7_FLEXSPI2(CCM_CCGR_ON);Which allows me to try things out, but this is a global change and as maybe not all PSRAMs are created equal,
and likewise I assuming that this same setting is used for QSPI Flash chips as well.
So, I was wondering if we should add an Api to core, that allows us to change it on a per sketch basis.
I currently experimenting in one of my sketches with a function that currently looks like:
C++:
void update_psram_speed(int speed_mhz) {
// What clocks exist:
static const int flexspio2_clock_speeds[] = { 396, 720, 665, 528 };
// See what the closest setting might be:
uint8_t clk_save, divider_save;
int min_delta = speed_mhz;
for (uint8_t clk = 0; clk < 4; clk++) {
uint8_t divider = (flexspio2_clock_speeds[clk] + (speed_mhz / 2)) / speed_mhz;
int delta = abs(speed_mhz - flexspio2_clock_speeds[clk] / divider);
if ((delta < min_delta) && (divider < 8)) {
min_delta = delta;
clk_save = clk;
divider_save = divider;
}
}
// first turn off FLEXSPI2
CCM_CCGR7 &= ~CCM_CCGR7_FLEXSPI2(CCM_CCGR_ON);
divider_save--; // 0 biased.
Serial.printf("Update FLEXSPI2 speed: %u clk:%u div:%u Actual:%u\n", speed_mhz, clk_save, divider_save,
flexspio2_clock_speeds[clk_save]/ (divider_save + 1));
// Set the clock settings.
CCM_CBCMR = (CCM_CBCMR & ~(CCM_CBCMR_FLEXSPI2_PODF_MASK | CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK))
| CCM_CBCMR_FLEXSPI2_PODF(divider_save) | CCM_CBCMR_FLEXSPI2_CLK_SEL(clk_save);
// Turn FlexSPI2 clock back on
CCM_CCGR7 |= CCM_CCGR7_FLEXSPI2(CCM_CCGR_ON);
}Kurt
