Teensy 4.1 with QSPI?


Well-known member
I need a QSPI Master interface (like regular SPI but with 4 data lanes).
I know, there is FlexSPI (for external memory, SPI flash chips or memory).

But I need the feature on regular LPSPI, to use PCS2 and PCS3 as DATA2 and DATA3.

So, does anybody know if for the SPI available on the header pins (marked as light green, e.g. MOSI1, SCK1, ...)
also the PCS2 and PCS3 signals are available?

BTW: FlexSPI as QSPI is potentially not available (with IOMUX and ALT config).
It would not help so much: I need a regular SPI with 4 serial data lanes (not all the INST, ADDR phases on FlexSPI).

Thank you.
(a spreadsheet with all the signal/pin names would be helpful, e.g. "GPIO_EMC_B2_16", so that I can lookup for the ALT functions
possible on the pins)
If you are excellent with soldering perhaps buying the TEENSY 41_NE Without the Ethernet Chip will do it.
U6 DP83825 Ethernet transceiver IC

PCS0 - routable to 2 pins    GPIO_B0_00 -- GPIO_B1_04
PCS1 - GPIO_B1_03
PCS2 - GPIO_B1_02
PCS3 - GPIO_B1_11
SCK - routable to 2 pins     GPIO_B0_03 -- GPIO_B1_07
SDi - routable to 2 pins     GPIO_B0_01 -- GPIO_B1_05
SDO - routable to 2 pins     GPIO_B0_02 -- GPIO_B1_06
TRG - routable to 46 pins, 62 signals
You can implement QSPI using FlexIO. Specifically FlexIO2 has two sets of four consecutive lines available (0-3, 16-19) and supports interrupts, DMA and external triggers (XBAR from other modules).
Thank you all.
Yes, I have checked the ALT functions for pins, starting at schematics.
Yes, if I would not have the ETH controller - the LPSPI4 would be able to do.

My (current) conclusions:
- LPSPI2 "could" do - but there is the external code flash memory (U3) - it is needed
- FlexSPI2_A could do - but would need to use the solder pads for PSRAM/Flash (the optional chips), and:
PCS2 (EMC40) would be missing! - it is the LDO_EN signal for the VHST (user host USB power LDO) plus PCS3 (EMC41) is not populated.
- LPSPI3: PCS2 (AD_B0_05) is not populated, PCS3 (AD_B0_06) is a signal on the "Boot Chip" - it is needed
- LPSPI4 conflicts just with PCS3 which is RXER on ETH controller:
Yes, a board w/o ETH and a wire from this pad - would work.
RX_ER on ETH could be used from EMC_26 - D0 on PSRAM (no optional chips)
- the SD Card is LPSPI1: similar to FlexSPI2_A: PCS2 (EMC_40) is LDO_EN and PCS3 (EMC_41) is not populated

So, I could use LPSPI4 with a rework on PCB - and no ETH controller, or:
wire ETH RX_ER but no optional PSRAM.

Best would be to redesign the PCB a bit - LOL:
- LDO_EN as VHST (on EMC_40) could be any other GPIO (not this one)
- EMC_41 (as PCS3) should be populated (it is not wired at all)
==> than I could use FlexSPI2_A (instead of PSRAM/Flash) or LPSPI1

Thank you all for the help.
I need a QSPI Master interface (like regular SPI but with 4 data lanes).
I know, there is FlexSPI (for external memory, SPI flash chips or memory).

But I need the feature on regular LPSPI, to use PCS2 and PCS3 as DATA2 and DATA3.

I'm curious which (non-memory) QSPI chip you're planning to use? Can you say the part number or give a link to its info?

Asking mostly because I'm not familiar with any chips using 4 bit SPI that aren't memory.
Hi Paul,
I am sorry, I cannot disclose details, just:
I need those MCUs in order to test new chips (under development, bring-up after production...).
So, my DUT (Device Under Test) will be such a (new) chip. Yes, it is not a memory chip, even using QSPI for fast transfer of data.

Using a MaaxBoard-RT - which can provide a full QSPI on user headers - I have seen that FlexSPI in NXP MCU is pretty cool:
it has a programmable "micro-engine" (LUTs) for QSPI, so that any vendor specific QSPI "protocol" can be implemented.
So, it should work, just an issue to have access to all the needed pins (Teensy 4.1 cannot).

keeping brainstorming with myself and FYI:
actually, the PSRAM and Flash (optional), provide a QSPI via FlexSPI2_A (with separate SS0_B and SS1_B).
This should work!
And solder pads are easy to access.
(why was I so complicated...?)

FlexSPIA, with the external code flash memory (U3) might work:
- use a parallel QSPI bus from this chip but with a SS1_B signal
- SS1_B is available on pin 22 - great
--> so, bring-out the QSPI bus on U3 (complicated) plus a separate SS1_B signal (and FW), would work as well.

All fine for now, looks promising: I will try to code my QSPI on optional PSRAM/Flash solder pads.

To be honest:
the AVNET MaaxBoard-RT cannot provide QSPI: I did a mistake on collecting needed signals
(SCLK and SS0_B are not available).
So, back to Teensy 4.1...
It would be far simpler to learn how to use FlexIO and the regular I/O pins... There's even master SPI sample code in the reference manual, you only need to change it slightly to output more bits in parallel.
I have QSPI working as "FastGPIO" as well as as "FLEXIO"
(on a different NXP MCU board, but it should work as well on Teensy 4.1 board)

QSPI with "FastGPIO":
I can generate a QSPI write with 40 MHz, potentially up to 60 MHz possible.

The MCU has also a feature called "FLEXIO": you can also implement any serial interface, even a serial-parallel interface with FLEXIO, e.g. QSPI.
And it works (on another board).

Teensy 4.1 FLEXIO:
I have checked the Teensy 4.1. schematics and pins: you have so many pins available for FLEXIO!
It would be even possible to connect an 8bit serial-parallel 8080 bus interface based LCD display!

Especially, the pins on extension header allow to use FLEXIO3 with AD_B1_00 ... AD_B1_15 (16x) plus B1_00 ... B1_03 (4x)
as "consecutive" pin use on FLEXIO (for "PARALLEL" mode).

So, you have so many pins available as FLEXIO that you could implement so many more I2C, SPI, UART, ... and even a serial-parallel interface
like for LCD-displays, other connections to other boards. And QSPI is also possible (but not drivers, examples available, except "my one").

The FLEXIO based implementation works fine up to 30 MHz, the next as 60 MHz might work as well, even it looks a bit "strange" in the waveform
(SCLK is not equidistant anymore, duty cycle is a bit "strange").

So, QSPI is possible on Teensy 4.1, with FLEXIO (and "FastGPIO"), just on/with the extension header pins
(no need to reuse the FlexSPI populated for the optional QSPI flash/RAM, which is also an option (Ion solder pads)).

That sounds super cool, thanks for your research on that!
@tjaekel, do you mind sharing a crude example of your QSPI setup using FlexIO? I feel a bit lost on how to approach this.

I was also planning on using the Teensy 4.1 to read out an ADC (AD4030-24). Reading 24 bits (plus up to 8 extra bits e.g. for common mode voltage) at 2 Msps requires a rather fast SPI – thus the AD4030-24 comes with a quad SPI (they call it a Flexi-SPI).
I'm a bit hesitant to use the i.MX RT1060's FlexSPI as the arbitrator might add a delay and uncertainty to the read-out and I don't know if the FlexSPI host controller is even designed for this custom protocol.

@tjaekel, you mentioned in a previous comment that using LPSPI might be an option. I don't see how that would work, or does LPSPI have an option for multiple data lines? I think it does support "double data rate" though.

Also, what do you mean with FastGPIO? Is that basically bit-bangning the interface in software?
Just as I posted this, I figured that there is indeed an option to have 4-bit transfers using LPSPI (see table 47-3, "WIDTH"). But as you discussed earlier, the four LPSPIs can't be configured for 4-bit transfer due to their pins being used elsewhere.
Hi, FYI,
I have FlexIO as QSPI working on a different NXP board. For this board I have also designed a PCB, like a HAT, to bring out SPI, QSPI, I2C, ... where QSPI and some GPIOs go via level shifters to external target (possible to set also for 1V2).
I am not sure, if I will try FlexIO QSPI on Teensy board, but I can share the FlexIO config and use (code) intended for a similar NXP MCU board.

FastGPIO means:
NXP MCU has option to use "tightly coupled GPIO", GPIOs which are accessed from CM7 directly. These are very fast: I can toggle GPIOs via SW (bit-bang-mode) up to 200...250 MHz. So, I have also an option to implement QSPI in GPIO mode (it just blocks all other threads when doing QSPI transaction, FlexIO would work in DMA mode and system remains responsive).

So, even Teensy 4.1 would not have a full blown QSPI FlexIO interface on pins available - it would require to have 4 consecutive GPIO pins available - there is still an option to use the FastGPIO pins and implement the QSPI fully in SW.
FastGPIO pins are all pins which are listed as GPIO_MUX2_IOxx or GPIO_MUX3_IOxx. There are two options to toggle a GPIO: regular or as FastGPIO (e.g. via GPIO8->PSR vs. CM7_GPIO2->PSR).
Hi @tjaekel

Thanks for your reply!
but I can share the FlexIO config and use (code) intended for a similar NXP MCU board.
That'd be great! If you have time, I'd be grateful if you could share your FlexIO config – I'm mostly struggling with how to approach the multiple data lines and shifting the date into one register.

Currently I'm considering using LPSPI1 for the 4-bit SPI. On the Teensy 4.1, the pins are used for the SD card and two pins are not connected (GPIO_EMC_40 and GPIO_EMC_41). This would require designing my own board, but that is something I considered anyway.

As for the other LPSPIs:
  • LPSPI2: Pins used for flash memory which I need
  • LPSPI3: Pins used by the boot rom as you already pointed out
  • and LPSPI4: Pins used by the ethernet, which I also need.
So as I don't need the SD card, the LPSPI1 seems to be the only viable option for me when it comes to implementing 4-bit SPI using the LPSPI controllers.

But maybe I can just use FlexIO, I'll have to try implement it in the coming days.
Just curious, did you make your own AD4030-24 circuit board? Or are you using the eval board? Or some other way of connecting the hardware?

In my dream world (of infinite hours in every day) we'd have drivers in Kurt's FlexIO_t4 library for all sorts of exotic ADC chips. Right now I'm working with MCP33131D for a special project, hope to publish code soon. For MCP33131D I built a first prototype with SMT adaptor boards and point-to-point wires soldered. Trying to bring it up on a custom PCB now....

did you make your own AD4030-24 circuit board
I'm currently working on that. The Analog Devices' evaluation board comes with a FMC (FPGA Mezzanine Card) connector which is a bit bulky for the Teensy and seems unnecessary for the relatively simple 4-bit SPI.

I previously built a custom board for the LTC2380-24 which is very similar to the AD4030-24 (it seems like the AD4030-24 is basically a version 2 of the LTC2380-24). As the older LTC2380-24 only has a single SDO, the SPI clock has to be quite fast to shift out all 24 bits (plus sometimes 8 extra bits) in between the conversion cycles at 2 Msps. I managed to reach speeds in the order of 1.5 Msps using LPSPI4, though I don't know how reliable the transfer actually is.

If I eventually use FlexIO for the AD4030-24, I'd be happy to contribute my code to Kurt's FlexIO_t4 library. Though I'm not yet certain on which interface (FlexIO or LPSPI1) to use. Either way, I'm happy to share my findings for anyone else trying to use the AD4030-24.
My FlexIO QSPI trial is here:

It is a MCUExpresso IDE project (not for Arduino, not for Teensy), based on the NXP SDK examples and drivers.
The target board is an AVNET Maaxboard-RT.
But you should be able to see how to extend a FlexIO SPI (as SDK example) to a FlexIO QSPI.

What to bear in mind:
You need four consecutive GPIO pins, with ALT for FLEXIO3_Dxx (or as FLEXIO2_Dxx), e.g. FLEXIO3_D24, FLEXIO3_D25, FLEXIO3_D26, FLEXIO3_D27. Via the configuration they are used as in a "concatinated way", so that a word in FIFO is spread over these data lanes. For SCLK and nCS you can use any other FLEXIOx_Dyy signal, as long as it is on the same FLEXIOx.
Check all the populated pins on Teensy board, if they have an ALT functions for FLEXIO (not all pins have).

The only issue where I have not found a "solution": how to change from a write to a read phase? Right now, write and read are two separate transactions. The FlexIO is reconfigured a bit to invert the direction for the read phase when the write has completed.
The drawback: the nCS signal generated by the FlexIO goes high in between (sure, two separate transactions). But it has to stay low between write and read phase. So, I have used a "software nCS" signal, as regular GPIO. Or: you "gate" this nCS signal generated by FlexIO, e.g. with an AND and a GPIO signal, in order to let the nCS stay low during the reconfig from write to read.

No idea how to use a "bi-directional" FLEXIO data line. Actually, I2C via FLEXIO should use such one (for SDA). But when the direction changes depend on the QSPI transaction. So, it is not hard-coded when the direction changes. Therefore, right now a WRITE and a READ transaction. Just make sure nCS stays low when direction changes (as GPIO signal).