Thread safety, please...

[PaulStoffregen]

If you call from an ISR a routine that itself does the disable -- enable sequence, you'll be returning to the ISR with interrupts enabled. Probably it will be ok.

On ARM Cortex-M, it will definitely be ok.

This is a common misunderstanding, based on knowledge of AVR or PIC, where interrupts are managed by a single global interrupt enable bit.

ARM chips have a far more sophisticated Nested Vector Interrupt Controller (NVIC). The PRIMASK bit allows interrupts when running interrupt code. It is NOT used by the NVIC to manage whether other interrupts can happen, as is done with the global interrupt enable by the very simplistic interrupt controllers on AVR and PIC. Which other interrupts can occur is done by priority management scheme within the NVIC.