obrienwhoi
New member
This is on a teensy 4.1
I have been pounding my head with ChatGPT for weeks on this. i have a 39 KHz signal on my FSYNC pin teensy pin 0. i have a 10 MHz signal on my DCLK pin teensy pin 27. pins 6,10,11,12,13,14,15,16 and pin 38 are used. i would like to take any other pin lets call it 'output pin' preferably pin 37 or 39 (next door to pin38) but not required and drive it high and low in hardware with this logic. on every rising edge of the FSYNC line i would like to drive output pin low and then start counting edges on the DCLK pin from 0. when DCLK count gets 192 edges i would like to drive output pin high. and then wait for the next rising edge on FSYNC. when it sees that next FSYNC rising edge it drives output low, resets the counter to zero and then counts to 192 again drives output high and so on and so on.
i am using LPSPI3 in slave mode as a shift register to shift in 24 bytes of data from my ADC to a ring buffer via DMA. i had this all working with interrupts and then found that when i was dumping ring buffer to uSD card my data was getting corrupt exactly during sd writes. i feel this is caused by the interrupt driven nature of the system at the moment. i would like all the data capture to be purely done in hardware but the LPSI shif register seems to need the chip select line to behave like a chip select line so i would like to try this aproach to drive the CS pin with another pin. if i can get this to work i think i'll be in business with no interrupts. all of the attempts with QTMR and DMA ISRs and FLEXIO and cross bar this to that have been failures. i can't even seem to get a simple proof of concept sketch working where i can check the expected pulse train and width on a scope. meaning strip everything else out and just see if you can get the above logic to create the desired output in the output pin. any help and a kick in the right direction and maybe example code would be greatly appreciated!
Thanks,
Jeff
I have been pounding my head with ChatGPT for weeks on this. i have a 39 KHz signal on my FSYNC pin teensy pin 0. i have a 10 MHz signal on my DCLK pin teensy pin 27. pins 6,10,11,12,13,14,15,16 and pin 38 are used. i would like to take any other pin lets call it 'output pin' preferably pin 37 or 39 (next door to pin38) but not required and drive it high and low in hardware with this logic. on every rising edge of the FSYNC line i would like to drive output pin low and then start counting edges on the DCLK pin from 0. when DCLK count gets 192 edges i would like to drive output pin high. and then wait for the next rising edge on FSYNC. when it sees that next FSYNC rising edge it drives output low, resets the counter to zero and then counts to 192 again drives output high and so on and so on.
i am using LPSPI3 in slave mode as a shift register to shift in 24 bytes of data from my ADC to a ring buffer via DMA. i had this all working with interrupts and then found that when i was dumping ring buffer to uSD card my data was getting corrupt exactly during sd writes. i feel this is caused by the interrupt driven nature of the system at the moment. i would like all the data capture to be purely done in hardware but the LPSI shif register seems to need the chip select line to behave like a chip select line so i would like to try this aproach to drive the CS pin with another pin. if i can get this to work i think i'll be in business with no interrupts. all of the attempts with QTMR and DMA ISRs and FLEXIO and cross bar this to that have been failures. i can't even seem to get a simple proof of concept sketch working where i can check the expected pulse train and width on a scope. meaning strip everything else out and just see if you can get the above logic to create the desired output in the output pin. any help and a kick in the right direction and maybe example code would be greatly appreciated!
Thanks,
Jeff