Yeah, I haven't updated the silkscreen in a couple of versions - I know them all by the layout.Your image says rev H in the title, but rev C on the silkscreen…
Your wish is my command. I'll post gerbers at some point, but the board image is about as good as it gets for now. The schematic will change a bit as I test 16x16 mode. I need to find out where resistors are needed in the signal leads with two boards mounted. At the moment the MCLK/BCLK resistors are populated near the Teensy and shorted out near the TLVs. I suspect the currently shorted resistors in the DI and DO lines will need populating in 16x16 mode, due to the additional trace length.Very cool! Is the full schematic / layout online anywhere to take a look?
The layout is fairly relaxed as I've been hand building with 0805 components. The other determining factor is that the number of input and output lines really determine the layout. I'll probably shift to 0603 on the prod version and reduce the track width from 11 mils to 9 or 10. That should allow closer packing. I've also got the clearance at 8 mils as that's a workable minimum for hand soldering.I notice the resistors and caps around the codec chips are pretty spaced out...
Good thought with open sourcing on JLC - that's probably the way to go. An issue with small-run PCBA is the cost of component wastage when not using standard parts. Probably not a big issue on this design as the TLV320 chips are the only non-standard items.Would be interested in ordering a board directly or from JLC whenever that becomes available.
With your multi TDM, what alternate sets of pins are you using for MCLK, BCLK, WCLK, DO and DI?I want to try out the ridiculous I/O count possibilities of my multi-TDM branch
My board uses MCLK=23, BCLK=21, WCLK=20, DO=8 and DI=7 (TLV-facing); DO=7, DI=8 (Teensy-facing).
I couldn't find the code on your github. Are you using common MCLK, WCLK?
If needed, I'll provide additional links on the board for those pins so that the alternates can be used for the alternate setup. (I've currently got links for DI and DO.)
Are the pins outlined by #AntiLoop in thread 7757 the ones you are using (Alt data pins = 6 & 32)?
Enough for now. Back to finishing the second prototype to test 16x16.