Updated 8x8 and 16x16 audio

Your image says rev H in the title, but rev C on the silkscreen…
Yeah, I haven't updated the silkscreen in a couple of versions - I know them all by the layout.

Very cool! Is the full schematic / layout online anywhere to take a look?
Your wish is my command. I'll post gerbers at some point, but the board image is about as good as it gets for now. The schematic will change a bit as I test 16x16 mode. I need to find out where resistors are needed in the signal leads with two boards mounted. At the moment the MCLK/BCLK resistors are populated near the Teensy and shorted out near the TLVs. I suspect the currently shorted resistors in the DI and DO lines will need populating in 16x16 mode, due to the additional trace length.

I notice the resistors and caps around the codec chips are pretty spaced out...
The layout is fairly relaxed as I've been hand building with 0805 components. The other determining factor is that the number of input and output lines really determine the layout. I'll probably shift to 0603 on the prod version and reduce the track width from 11 mils to 9 or 10. That should allow closer packing. I've also got the clearance at 8 mils as that's a workable minimum for hand soldering.

Would be interested in ordering a board directly or from JLC whenever that becomes available.
Good thought with open sourcing on JLC - that's probably the way to go. An issue with small-run PCBA is the cost of component wastage when not using standard parts. Probably not a big issue on this design as the TLV320 chips are the only non-standard items.

I want to try out the ridiculous I/O count possibilities of my multi-TDM branch
With your multi TDM, what alternate sets of pins are you using for MCLK, BCLK, WCLK, DO and DI?
My board uses MCLK=23, BCLK=21, WCLK=20, DO=8 and DI=7 (TLV-facing); DO=7, DI=8 (Teensy-facing).
I couldn't find the code on your github. Are you using common MCLK, WCLK?
If needed, I'll provide additional links on the board for those pins so that the alternates can be used for the alternate setup. (I've currently got links for DI and DO.)

Are the pins outlined by #AntiLoop in thread 7757 the ones you are using (Alt data pins = 6 & 32)?

Enough for now. Back to finishing the second prototype to test 16x16.
 

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With your multi TDM, what alternate sets of pins are you using for MCLK, BCLK, WCLK, DO and DI?
My board uses MCLK=23, BCLK=21, WCLK=20, DO=8 and DI=7 (TLV-facing); DO=7, DI=8 (Teensy-facing).
I couldn't find the code on your github. Are you using common MCLK, WCLK?
If needed, I'll provide additional links on the board for those pins so that the alternates can be used for the alternate setup. (I've currently got links for DI and DO.)

Are the pins outlined by #AntiLoop in thread 7757 the ones you are using (Alt data pins = 6 & 32)?
The clock signals are all commoned, with just data pins changing according to the usual SAI1 scheme, so using 7, 32, 9 and 6 for Teensy out, 8, 6, 9 and 32 for in. You have to use the pins sequentially (no using just 7 and 9 for 2x outputs, must be 7 and 32), and obviously they’re unidirectional! Four of your boards would fully use 7+8 and 32+6, and two more would be half-used on pin 9 as either inputs or outputs. Use TDM2 as well for total ridiculosity.

My opening post in that thread has the link to the relevant code branch, which includes an updated Design Tool allowing you to place the new TDM objects, signalling any clashes, and with documentation in the info pane on the right hand side. (It doesn’t enforce the sequential pins rule, have to consider if that’s possible…) Please post on that thread if you have issues or questions about my code, or of course here if it seems more relevant to your hardware. I’ll pick up on it either way.

TDM uses quite a lot of audio blocks, so do keep an eye on AudioMemory use.
 
Yeah, I haven't updated the silkscreen in a couple of versions - I know them all by the layout.


Your wish is my command. I'll post gerbers at some point, but the board image is about as good as it gets for now. The schematic will change a bit as I test 16x16 mode. I need to find out where resistors are needed in the signal leads with two boards mounted. At the moment the MCLK/BCLK resistors are populated near the Teensy and shorted out near the TLVs. I suspect the currently shorted resistors in the DI and DO lines will need populating in 16x16 mode, due to the additional trace length.


The layout is fairly relaxed as I've been hand building with 0805 components. The other determining factor is that the number of input and output lines really determine the layout. I'll probably shift to 0603 on the prod version and reduce the track width from 11 mils to 9 or 10. That should allow closer packing. I've also got the clearance at 8 mils as that's a workable minimum for hand soldering.


Good thought with open sourcing on JLC - that's probably the way to go. An issue with small-run PCBA is the cost of component wastage when not using standard parts. Probably not a big issue on this design as the TLV320 chips are the only non-standard items.


With your multi TDM, what alternate sets of pins are you using for MCLK, BCLK, WCLK, DO and DI?
My board uses MCLK=23, BCLK=21, WCLK=20, DO=8 and DI=7 (TLV-facing); DO=7, DI=8 (Teensy-facing).
I couldn't find the code on your github. Are you using common MCLK, WCLK?
If needed, I'll provide additional links on the board for those pins so that the alternates can be used for the alternate setup. (I've currently got links for DI and DO.)

Are the pins outlined by #AntiLoop in thread 7757 the ones you are using (Alt data pins = 6 & 32)?

Enough for now. Back to finishing the second prototype to test 16x16.

Thank you for sharing!

Interesting, I would have figured there would be some sort of daisy chain configuration for the codecs but it appears TDM is wired to all the chips in parallel.

How is that working in software? By what mechanism are the codecs assigned which part of the TDM data they interact with?

Seeing these two sections in the online documents but neither seems to give a full description of the register and how it's supposed to be working 🤔

It also looks like you're having to multiplex I2C in some way because the codec doesn't have address pins which is funny. Is that just an inherent limitation of this chip?

Do you have a Teensy Audio Library style control object written? Or is that still in the works?

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Additional note: if the application was skewed towards many inputs or many outputs, then one would need more half-used boards. 80 inputs and 32 outputs needs 10 boards, 6 of which are inputs-only.
 
Thank you for sharing!

Interesting, I would have figured there would be some sort of daisy chain configuration for the codecs but it appears TDM is wired to all the chips in parallel.

How is that working in software? By what mechanism are the codecs assigned which part of the TDM data they interact with?

Seeing these two sections in the online documents but neither seems to give a full description of the register and how it's supposed to be working 🤔

It also looks like you're having to multiplex I2C in some way because the codec doesn't have address pins which is funny. Is that just an inherent limitation of this chip?

Do you have a Teensy Audio Library style control object written? Or is that still in the works?

I’ve done the Audio library software, tested on CS42448 and PCM3168 codecs so far.

Most of the hardware is indeed in parallel, but the data pins are not, so you set up the hardware to use the right pins, and pick the software audio objects that route to those pins. The original TDM used just pin 7 for output, 8 for input; the new update adds AudioOutputTDMB for output on pin 32, and so on.

Early TDM development gave 16x 16-bit channels per pin, but the above parts restrict you to 8x channels, hence the weird rule about only using the even-numbered ports on the audio objects. With these boards we’ll be able to use all 16 ports. @palmerr will have to provide the relevant control object to allocate which 8 of the 16 channels are used on any given board.
 
#grinch

Yes, you have picked the appropriate manual sections - along with DSP mode in Register 9.

HiZ is exactly as described. Each chip puts its DO pin in HiZ mode when not actively transmitting.

It will transmit the number of bits in Reg 9, offset by the value (BCLKS) in R10. Simple, really.

BCLK needs inverting and the the offsets increased by 1 to make the timing right. Other combinations may work, but I haven't had success with the obvious BCLK not inverted and offset = 0.

I2C is multiplexed as shown on the posted schematic.

Yes, there is a Teensy Audio Lib control, object. It works in 8x8 and 16x16 mode and I'm tidying it up at the moment.
 
Couple of things on the rev H hardware…
  • we’re restricted to 4 boards by the I2C multiplexer; could you link the SDA/SCL pins, so we can use one of the other I2C buses? It’s likely a rare use-case, so a full set of jumpers is overkill - I’m happy to bodge the wiring to test this :)
  • it looks as if you’re using pin 13 for reset (?). As that’s the on-board LED and also the main SPI SCK signal, that’s not a great choice. Apologies if I’m misreading your schematic…
 
#grinch

Yes, you have picked the appropriate manual sections - along with DSP mode in Register 9.

HiZ is exactly as described. Each chip puts its DO pin in HiZ mode when not actively transmitting.

It will transmit the number of bits in Reg 9, offset by the value (BCLKS) in R10. Simple, really.

BCLK needs inverting and the the offsets increased by 1 to make the timing right. Other combinations may work, but I haven't had success with the obvious BCLK not inverted and offset = 0.

I2C is multiplexed as shown on the posted schematic.

Yes, there is a Teensy Audio Lib control, object. It works in 8x8 and 16x16 mode and I'm tidying it up at the moment.

How does 16x16 mode work with the I2C multiplexing? It seems like each codec chip needs its own multiplexer channel and there are currently only 4? Do you use a different I2C line or set it up with a different multiplexer?
 
Jonathan,

I'll free up the other MUX address pin for you to allow 32 channels. However, it is likely that the TDM bus loadings and signal reflections will defeat you before you get there!

You are correct on the reset pin. I'll change it to something relatively free of other uses - any suggestions of a nearby pin? 14 looks like a good candidate.
 
Pins 14 and 15 are S/PDIF, but although I managed to make them a clock master for I2S I think it may not be possible for TDM. Pin 22 is completely free, but further to route.

Oops! 8 Mux addresses = 64 audio channels!
Oh yes! I was going by your schematic comment… I think that does it … 8 boards with all 64 outputs used, and a couple of those give you 16 inputs … or vice versa … or 5 boards for 32i48o. Check my maths, please :unsure:

Yes, point taken about loading and reflections. Looks like the PCBAs from JLCPCB will omit the connectors? That’s good, at least they can be stacked very close together.

Hmm … have you measured the power consumption of each board? Looks like the TLV320 is quite low compared to some of the 6i8o parts.
 
Yes, JLCPCB will be without connectors. For software testing only the Teensy headers are needed - but they can be short or long pinned, dependent on stacking.

The crossed out DI/DO resistors are TBC once I get a bit further into testing 16x16. I suspect they will be necessary with two or more stacked boards. 8x8 works fine with them shorted out.

The MCLK and BCLK resistors for each CODEC are unlikely to be needed, and will disappear if 16x16 testing proves this true. 8x8 works fine with them shorted out.
 
I have ordered 10 PCBA boards from JLCPCB to ensure everything is correct. They cost $100 US, without headers, including $15 postage to Australia.

I also added an optional -5V rail generator on the rear of the board for those applications that need more output swing ( 8+8V p-p balanced, instead of 2+2V).

I will make the excess (~6) available on Tindie (https://www.tindie.com/products/palmerr223/teensy-8x8-audio-board/) and make the project public on JLCPCB once everything is checked.

I also have "wing" boards with audio (TRS, XLR, COMBO) connectors on them for folks who want to use them in projects, rather than just exploring the capabilities of the hardware and software.

I have created a repo which will have a set of driver files, PCB files and documentation.
https://github.com/palmerr23/Teensy8x8AudioBoard
Nothing is there as yet!
 
Good news! Hope they work as expected: given the effort you’ve put in I’d be surprised if they don’t. $100 including shipping seems very reasonable, though they’ll probably be a bit more in the UK because VAT will be added on. Unless the same is true for AU as well…

Currently thinking I’ll hold off and order a batch from JLCPCB. Once I’ve had my fun there may be a few lightly-used ones for sale in the UK :)

Oh, and your Tindie link is broken, looks like the open bracket got mixed into the URL.
 
Oh sheessh... happened to me once. Forgot to make visible the ground planes when exporting and there wasn't on the gerbers, a real pain. When ordering on JLCPCB you can open a gerber viewer to check layer by layer. I recommend you to do so every time you order to ensure everything is ok, more than once I spotted this kind of mistakes before ordering.
 
Yes, I checked both on the Kicad Gerber viewer and JLCPCB PCBA tools and simply missed that I hadn't unchecked the "don't fill areas" option on the JLCPCB Tools settings page. C'est la vie!

The benefit for others is that I was working on an alternate version with reduced the board size by rotating the CODECS 45 degrees and moving some other components around. I think I'll be able to shave off 15mm from the length and possibly 10mm from the width, as the original board had provision for using pin 32 on a T4.1 as an alternate TDM pin and had input and output capacitors mounted. The capacitors have now moved to the I/O 'wing' boards, and there are enough alternate pins (I hope) on a T4.0 to satisfy h4yn0nnym0u5e's multi-channel TDM driver.
 
Looks like the multi-TDM will still work, "pin" 32 becomes a pad on the bottom of Teensy 4.0. I have a preference for Teensy 4.1 for audio, because it's easy to use the SD socket for extra speed when doing file playback and recording, and it has the PSRAM pads. I've never tried fitting a socket to a 4.0, but imagine that's fiddly. And there's no substitute for the PSRAM :(. Or the Ethernet, come to that, though I've never used it.

Presumably there's nothing to stop a 4.1 being put on the new layout, apart from it overhanging the edge?
 
The new T4.1 overhang is only a few millimetres. All that would be required to use Pin 32 will be a short flying lead from the DI or DO jumper. A duPont connector would work nicely. BTW, I've never had much success using pogo pins to the bottom pads on Teensy's.

I use Ethernet audio reasonably often, as it's the only way to get more than 2 audio channels to a PC. Also, this new board would make a nice digital snake, or even something that could distribute stereo pairs to multiple slaves (or vice-versa) over ethernet. All that's working now with my Ethernet Audio library and there is an example file in the control library.
 
Perfect. An overhang is actually quite nice, as it means you can get the SD slot right up to the case wall, and access it from outside. I’d rather run USB a bit further than SDIO….

Never needed to go the pogo pin route, but if I’m ever tempted I’ll bear your experience in mind … thanks :)
 
Wow on all the recent developments! Sorry to hear about the missing ground plane, I'm very interested in one of your pre-assembled boards once you get the revised version. Like very very interested.
 
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