using PSRAM with SPI1 instead of SPI2

[mark63]

The external SRAM looks great. But i need all the UARTS so i can not use it. Is there i way i connect a chip to SPI1 hardware which is free? I assume this is possible? But which files to modify and where are they?

 

[defragster]

Is this PSRAM for use on a T_4.1?

If so the QSPI pads on the underside for PSRAM do not use any SPI pins - it maps to unique Quad SPI pins direct to the processor.

 

[BriComp]

With all due respect, what are you talking about?
What external SRAM?
What are you trying to do?
What chip are you trying to attach to SP1 hardware?

 

[mark63]

thanks for the replies. yes this is about the T4_1. It has provision for a 8MB RAM chip which can be used as external RAM. This is great but i need all the TX/RX and using the pads on the T, i will loose that functionality right? I mean TX1, RX1 and RX8.
So the idea is to use SPI 1 (MOSI1, MISO1, SCK1) . But from the first reply it seems that is only possible when SPI1 is quad spi?
So to answer the other questions : the PSRAM on the bottom of the T4_1. This is external SRAM right? (internal dynamic).
What i try to do is to have a lot of external RAM.
I do wonder if this QSPI is so special, am i right that once enabled i lose the TX/RX functionality?
The problem with all processors is that they have many options but too little pins so you always need to chose.

 

[defragster]

See if reading p#2 again makes sense ... No SPI 1 or SPI 2 or any other pins or PRIMARY pin functions are shared with those bottom side pins.

There are 'light gray' optional alternate functions shown for other indicated 'bus' - but unless those pins are selected, they are not the primary pins use.

If those pins are used for alternate functions, then the QSPI features for PSRAM will not be available elsewhere. QSPI uses 4 data transfer pins versus a single data transfer pin for MOSI and MISO.

 

[PaulStoffregen]

will loose that functionality right? I mean TX1, RX1 and RX8.

No, you don't loose serial functions by using PSRAM. My guess is you're misunderstanding this info:



These pins are alternate locations for TX1, RX1, RX8.

You can still use them at their normal default locations on pins 1, 0, 34.



The alternate locations are rarely used. But they can be handy in some situations. For example, if you *really* needed to use all 3 CAN ports, then pins 0, 1 would be used since CRX2 and CTX2 have no alternate locations. But RX1 and TX1 do have alternate locations on the PSRAM pins. That is the sort of scenario where someone might make use of the alternate RX1 and TX1.

You would lose Serial1 functionality if you needed to use CAN port 2 (consuming the normal RX1 & TX1 pins) and also PSRAM (consuming the alternate RX1 & TX1 pins).

 

[PaulStoffregen]

You can also get more serial ports using FlexIO. The main limitation with FlexIO used as serial is lack of support for slow baud rates. As I recall, it only has an 8 bit counter to divide the clock to get the baud rate.

 

[mark63]

thanks for the replies. i am glad i asked since indeed Paul, i misunderstood this info. Now i look better and compare with the other side of the card i see that the color is different and these are alternative pins.And that means that i can also use the SD card as it seems. That is just great.

 

[mark63]

See if reading p#2 again makes sense ... No SPI 1 or SPI 2 or any other pins or PRIMARY pin functions are shared with those bottom side pins.

There are 'light gray' optional alternate functions shown for other indicated 'bus' - but unless those pins are selected, they are not the primary pins use.

If those pins are used for alternate functions, then the QSPI features for PSRAM will not be available elsewhere. QSPI uses 4 data transfer pins versus a single data transfer pin for MOSI and MISO.

thanks. i think it was the heat but i did not get it. it took Pauls reply to get it. Now i know it makes perfect sense. A picture says more than 1000 words, especial for the slow ones like me . i better get a new prescription for glasses.