Using "SDIO2" for SdFat (SD card)

[Dogbone06]

Hey!

Trying to figure out where and how to change the SDIO pins to use SDIO2 instead.

The SdFat library only has the pin mentions in one file. But it feels like it can't be that easy. As they are only MUX settings. How will the library know where to "send the data". So I think I'm missing something.

SdioTeensy.cpp

Wanna use these pins instead or actually maybe even use both busses for two SD Cards.
AD_B1_06: DAT2
AD_B1_07: DAT3
AD_B1_08: CMD
AD_B1_09: CLK
AD_B1_04: DAT0
AD_B1_05: DAT1

 

[jmarsh]

The pins aren't used directly, all the programming is done via the USDHC interface which is hardcoded to USDHC1: https://github.com/PaulStoffregen/SdFat/blob/master/src/SdCard/SdioTeensy.h#L231

Some of the clock configuration might need to be changed too since each module usually has its own bits in the CCM registers.

 

[Dogbone06]

Thank you! Rezo and I will take a look at this and see, Rezo has a breakout SD card slot so it can be tested.

 

[KurtE]

As mentioned:

All of the registers access are hard code to 1... Like in SdioTeensy.h you have:

#define SDHC_DSADDR       (USDHC1_DS_ADDR ) // DMA System Address register
#define SDHC_BLKATTR      (USDHC1_BLK_ATT) // Block Attributes register
#define SDHC_CMDARG       (USDHC1_CMD_ARG) // Command Argument register
#define SDHC_XFERTYP      (USDHC1_CMD_XFR_TYP) // Transfer Type register
#define SDHC_CMDRSP0      (USDHC1_CMD_RSP0) // Command Response 0
#define SDHC_CMDRSP1      (USDHC1_CMD_RSP1) // Command Response 1
#define SDHC_CMDRSP2      (USDHC1_CMD_RSP2) // Command Response 2
#define SDHC_CMDRSP3      (USDHC1_CMD_RSP3) // Command Response 3
#define SDHC_DATPORT      (USDHC1_DATA_BUFF_ACC_PORT) // Buffer Data Port register
#define SDHC_PRSSTAT      (USDHC1_PRES_STATE) // Present State register
#define SDHC_PROCTL       (USDHC1_PROT_CTRL) // Protocol Control register
#define SDHC_SYSCTL       (USDHC1_SYS_CTRL) // System Control register
#define SDHC_IRQSTAT      (USDHC1_INT_STATUS) // Interrupt Status register
#define SDHC_IRQSTATEN      (USDHC1_INT_STATUS_EN) // Interrupt Status Enable register
#define SDHC_IRQSIGEN     (USDHC1_INT_SIGNAL_EN) // Interrupt Signal Enable register
#define SDHC_AC12ERR      (USDHC1_AUTOCMD12_ERR_STATUS) // Auto CMD12 Error Status Register
#define SDHC_HTCAPBLT     (USDHC1_HOST_CTRL_CAP) // Host Controller Capabilities
#define SDHC_WML        (USDHC1_WTMK_LVL) // Watermark Level Register
#define SDHC_MIX_CTRL     (USDHC1_MIX_CTRL) // Mixer Control
#define SDHC_FEVT       (USDHC1_FORCE_EVENT) // Force Event register
#define SDHC_ADMAES       (USDHC1_ADMA_ERR_STATUS) // ADMA Error Status register
#define SDHC_ADSADDR      (USDHC1_ADMA_SYS_ADDR) // ADMA System Addressregister
#define SDHC_VENDOR       (USDHC1_VEND_SPEC) // Vendor Specific register
#define SDHC_MMCBOOT      (USDHC1_MMC_BOOT) // MMC Boot register
#define SDHC_VENDOR2    (USDHC2_VEND_SPEC2) // Vendor Specific2 register
//

Likewise IRQ:

#define IRQ_SDHC    IRQ_SDHC1

Not sure about DMA, if there is anything to change (Other than registers).

 

[PaulStoffregen]

Wouldn't hurt to reach out to Bill Greiman (author of SdFat library) and offer to send him the hardware, if you have an extra board.

 

[Dogbone06]

Will try to reach Bill Greiman and see what he says.

 

[jmarsh]

IIRC this is possible with a T4.1? Since that's where the idea of using the second port originated. There's probably a good chance he has an SD breakout already.

 

[Dogbone06]

IIRC this is possible with a T4.1? Since that's where the idea of using the second port originated. There's probably a good chance he has an SD breakout already.

Sounds promising, I have contacted him.

 

[jmarsh]

Slightly related but also off-topic: it would be nice to know what the other USDHC pins are for (the ones that aren't DATX, CMD or CLK). I haven't seen any reference to them in the IMXRT manual. I can take a guess that "WP" is a write-protect pin but how is it supposed to function?