What does this tell you about my SPI signal?


Well-known member
I'm trying to get an LCD panel working with a custom T4.1 device, but I'm getting mostly garbage on the screen, so I'm thinking I have signal integrity issues. Here's a pic of the SPI CLCK on my oscilloscope.

I'm guessing I can slow down the SPI interface and get the LCD working properly, but I'm more curious about what this says about how I have things wired up. It almost looks like there's a capacitor on the line. What can cause this kind of issue? Could my traces be too long or too thick? Could SPI CLCK line being too close to other traces account for this?
Ah yes, good call on the probe setting.


I didn't even think of this because my scope's probes (Keysight N2894A) don't have a 1X vs 10X mode switch.
Thanks guys. I switch to 10x and it's looking more realistic. Now I'm seeing a significant amount of ringing. I suspect this could be the cause of my issue?

When it comes to this, and really fast signals, the layout on the board also plays a role. But i'm sure the lcd is well below 100MHz, more likely 30..60MHz max.

I'm trying to get an LCD panel working [...]
Could SPI CLCK line being too close to other traces account for this?

Just try to keep the layout of faster signals short.
50MHz will be pushing it without transmission-line / impedance controlled signals. To run a 3.3V single-ended logic signal impedance-matched requires 30 to 60mA, which is why things break down at higher speeds where stray impedances are measured in low hundreds of ohms. LVDS is extensively used for higher speed logic as its both differential and low-voltage/low-current. The low voltage makes the power consumption plausible, differential maximizes the chance of clean reception in the face of signal degradation, and allows it to go off-board easily (laptop screens extensively use LVDS over 4 to 8 pairs).

So without LVDS stick to 30MHz tops for a good chance of success...