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  • Jay8ee's Avatar
    01-16-2021, 10:45 PM
    Thanks for the reply. The pin is actually one pin further to the right (B8), but the photo kinda makes it seem like it is in the +3.3v out (which is not a port). Thanks for the heads up though.
    9 replies | 266 view(s)
  • Jay8ee's Avatar
    01-16-2021, 10:08 PM
    Here is the picture of the connections between my Teensy and the FPGA dev board I am using as a logic analyzer (it is an Alchitry AU) So I just put a wire between my FPGA and the Teensy and now it works...
    9 replies | 266 view(s)
  • Jay8ee's Avatar
    01-16-2021, 12:47 AM
    Thanks for the reply. Those are pretty much the full picture, there's not really anything omitted from them. I'll try to snap some pics of the hw setup in the morning when I have better light. The FPGA is sampling at...
    9 replies | 266 view(s)
  • Jay8ee's Avatar
    01-15-2021, 10:50 PM
    Hello. I'm using Teensy as an SPI master for a project I am working on, but I am having some trouble getting reliable data transmission working. I am seeing the transmitted byte corrupted approximately 50% of the...
    9 replies | 266 view(s)
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Irregular SPI Behavior 01-16-2021 10:45 PM
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06-25-2019