miciwan
Junior Member

Yup, they cannot generate DMA requests (or rather they most likely can, it's just not routed to the DMA Mux). With the interrupts I've been generally seeing some weird stuff going on. Enabling them for any shifter does...

Nice! @easone do you happen to remember what problems you had when using the shifters 4-7? In my experiments, they were behaving just fine, but I haven't tested them really thoroughly. BTW, in the SmartMatrix code,...

The manual is indeed pretty inconsistent. Most of the sections just talk about SHIFTERi. The text description of the parallel interface in 50.3.4.1 mentions shifters 0-7, and so does the example setup of the Motorola...

Sure - just a signal analyzer hooked up straight to Teensy. But the ground was a good direction! Thanks for that tip! I did connect ground in few more places rather than only two, and it totally helped. Below...

There's no PCB, it's just the logic analyzer/signal generator hooked up to Teensy pins. And the same thing happens at lower speeds too. With 12bit bus, I'm seeing these glitches even at 1MHz. And on the other hand, even...

I tried doing similar setup for the output and it works fine too. I set up the FlexPWM module to ouput the clock signal on Teensy pin 4 (should be doable with QuadTimer too, but FlexPWM docs were easier to parse...) -...

@KurtE - ah, great points. Properly flushing/invalidating caches is crucial when working with such systems, thanks for pointing that out. TBH, with this being my first T4.1 thing that I touched, I haven't even noticed...

I was going through the DMA related things recently, starting from scratch, and I was writing things up as I went through them. I posted the thing here:...

Hi everyone, I have recently started looking into using some of the lower-level functionality of the Teensy 4.1/iMX RT 1060, including DMAs, register-level access to pins etc, and eventually landed here. Up until...