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  • Neal's Avatar
    Yesterday, 05:12 PM
    I got my replacement Audio board running and reran my tests. I reconfirmed that Paul's observations are accurate in my test setup as well. The ADC transmits 24bits regardless of the CHIP_I2S_CTRL register data length...
    8 replies | 191 view(s)
  • Neal's Avatar
    03-01-2021, 05:44 PM
    Thanks for the responses. Paul I did the same test you did with two exceptions. I bypassed the line in and line out series capacitors and fed in a very clean DC signal into the ADC and measured the DAC DC output signal....
    8 replies | 191 view(s)
  • Neal's Avatar
    03-01-2021, 04:25 PM
    Yes I realize that the it is only spec'd to 96 kHz. I guess I was hoping there was some magical overdrive mode. The real dilemma I am having is that it appears the sgtl5000 ADC outputs 32 bits and the DAC accepts 32...
    8 replies | 191 view(s)
  • Neal's Avatar
    02-28-2021, 04:30 PM
    In my application, everything I am using 32 bit integers exclusively. I would like to use the 32 bit mode in the sgtl5000 as well. As far as I can tell the following lines of code from the i2s library are already...
    8 replies | 191 view(s)
  • Neal's Avatar
    02-20-2021, 04:10 PM
    Can you point me to a TI audio codec similar to the sgtl5000 that has more information on the decimation and reconstruction filters?
    24 replies | 738 view(s)
  • Neal's Avatar
    02-20-2021, 04:08 AM
    I finally found a bit of time to dig into this a little further. I wanted to find out how much of the 250 usec could be attributed to just the DAC. So I measured the time it took from an i2s write to the time the DAC...
    24 replies | 738 view(s)
  • Neal's Avatar
    02-12-2021, 11:26 PM
    The total delay is 250 usec when input and output are viewed on an oscilloscope. Since the sampling frequency is 96000 Hz, that is about 24 sample times. This is basically a black box test, so I have no idea how much of...
    24 replies | 738 view(s)
  • Neal's Avatar
    02-12-2021, 06:29 PM
    As a point of reference, the 250 usec delay I measured in my testing is about 24 sample delays because my test was at Fs = 96000 Hz. It is an 11 sample delay at Fs = 44100. The TI document is well written, as we are...
    24 replies | 738 view(s)
  • Neal's Avatar
    02-11-2021, 12:29 AM
    Here is a much better explanation than the one I gave. https://web.ece.ucsb.edu/~yoga/courses/DSP/P10_Linear_phase_FIR.pdf
    24 replies | 738 view(s)
  • Neal's Avatar
    02-11-2021, 12:27 AM
    No, I mean linear phase delay. For example, if you have a signal that is made up of say a 1 Hz tone and a 2 Hz tone and you are going to feed them into a linear phase FIR filter. Both signal components will be delayed...
    24 replies | 738 view(s)
  • Neal's Avatar
    02-08-2021, 04:54 PM
    I did more tests over the past few days and the results are consistent with the above assumptions of there being a FIR filter somewhere in the processing chain. I tested the delays over for various frequency sine waves...
    24 replies | 738 view(s)
  • Neal's Avatar
    02-05-2021, 09:48 PM
    Your post is a few months old, but I have two questions: 1. Can you point me to a link that documents the -Wl,--print-memory-usage option? 2. How did the output it generated compare to the output KurtE was getting?...
    172 replies | 19252 view(s)
  • Neal's Avatar
    02-04-2021, 07:14 PM
    Yes I agree the architecture is probably sigma delta. Also, at a 10.4 usec conversion rate, the delay is about 25 sample times. FIRs can eat that up, but IIR CIC filters that are usually used after a sigma delta...
    24 replies | 738 view(s)
  • Neal's Avatar
    02-04-2021, 04:21 AM
    I wrote a simple program to try and understand a 250 usec delay I am seeing between the sgtl5000 input to its output. The intent of this test is to take a single sample from the codec ADC into the teensy and then send...
    24 replies | 738 view(s)
  • Neal's Avatar
    01-21-2021, 10:16 PM
    Thanks for taking care of that. Good solution.
    5 replies | 350 view(s)
  • Neal's Avatar
    01-21-2021, 10:03 PM
    I don't think it is necessary to change any source code. It would be nice to include it in errata documentation somewhere if an errata exists. I just reversed things in my project code. I pointed it out so it might...
    5 replies | 350 view(s)
  • Neal's Avatar
    01-21-2021, 04:25 PM
    FYI-Here is a very small item that caused me some confusion while using the sgtl5000 Audio Library routines. I did not find it mentioned anywhere in the forum so I thought I would document it for reference. The...
    5 replies | 350 view(s)
  • Neal's Avatar
    01-17-2021, 04:53 PM
    Frank-My uP is a T4.1 and the Memory wipe procedure shown on the teensy 4.1 page solved the problem. Memory Wipe & LED Blink Restore Teensy 4.1 will fully erase its non-volatile memory and return the flash memory to...
    15 replies | 654 view(s)
  • Neal's Avatar
    01-16-2021, 05:58 PM
    I wanted to play with this a bit so I temporarily added this line of code into the main loop(): if(digitalReadFast(29) == LOW) SCB_AIRCR = 0x05FA0004; Now, even with removing that line of code I can no longer...
    15 replies | 654 view(s)
  • Neal's Avatar
    01-11-2021, 05:17 PM
    "On / Off Pin and Power Control" is mentioned at https://www.pjrc.com/store/teensy41.html. Is there a pad somewhere on the Teensy 4.1 PCB to access the ON/OFF connection to the microprocessor? I can't find it anywhere....
    8 replies | 374 view(s)
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