It's the same as usual (DMA memory access is basically the same as the CPU since there's no MMU) except with those memory regions you'd need cache management - flush any source memory from the CPU's cache before the...
That doesn't seem like the logical way to do what is desired; rather it sounds like you should be transmitting the mouse data in a separate timed loop if that's what the FPGA requires.
Twos complement is just the typical number format used by machines.
From the MPU6050 register map and descriptions datasheet:
-2857 / 340 + 36.53 = 28.127 degrees celsius = 82.63 degrees F.
My reply was...
Looking at the color lines of the circuit with fresh eyes, I think it could be simplified to get rid of four resistors?
/*
* INTENSITY (13) <-- 536R --\
* |
* GROUND <------ 536R...
I'll try and explain it a bit better.
So you've got all the SDO signals coming out of the DACs, all going in to one input on the Teensy. According to the DAC datasheet, the SDO pin is only driven when the corresponding...
No.
The DMA hardware doesn't actually care about the alignment (other modules might, but DMA doesn't). The restriction comes from the CPU's 32-byte length cachelines - if your arrays aren't aligned to the start of a...
That would be the IPG bus clock mentioned earlier. It's always one quarter of the main CPU clock (default CPU clock = 600MHz, so default IPG = 150MHz).
Then you're going to have to change it, because it's not going to work; you can't tie the outputs from the A side of the level shifters together (the signal that connects to pin 12 on the Teensy) without any extra...
This is not clear. Are the connections as shown in your image, or are they not? How can we help you if we're not shown the correct information?
We need full details of how all chips in the project are connected, not...
TBH I'm not sure I understand the wiring, why have 13 level shifters that are mostly translating identical signals (SCK/SDI/SDO) with only one unique line (CSx) per chip.
If all the SDO outputs from the level shifters are connected together and their OE is connected to constant 5V, they're all driving that line at the same time - shorting 3.3V to GND if one tries to output HIGH and...
CITER and BITER are still set to 3, so it's looping 3 times and then moving the source/destination pointer back 5 words. Eventually it's probably overwriting something important.
Maybe I'm missing something but 74x244s aren't going to buffer like that... they don't latch their input values, they only let you tri-state the outputs. You will still only be able to send 8 bits maximum at any point...
Technically it is one instruction, but not every instruction takes one cycle/tick.
The quad timers use the IPG clock (150MHz) so any access to their registers from the CPU has to be synchronized to that, so there's at...
The PAD control registers (where hysteresis, pull-up/downs etc are configured) are completely separate from the mux settings (which determines which module the pin is routed to), so I don't see why this wouldn't work. I...
Unfortunately not. Due to limitations of this particular ARM CPU, as soon as you write any value it will read the existing cacheline from memory (to preserve the unwritten portion). There's no way around this even if...
The FlexSPI module (used to map the PSRAM chip to memory) has internal buffers for prefetching, when a read happens it will automatically fill the buffer by doing SPI reads to read ahead. This comes at basically no...
Increasing the clock speed will give the best results (there are posts on this forum with the details) and you can also try turning on prefetching: https://github.com/PaulStoffregen/cores/pull/708
It depends exactly how you're doing the buffering.
If you copy the full frame to be rendered into PSRAM during vsync, that will probably work fine. But if you try to write to PSRAM during rendering, there won't be...
It would be far simpler to learn how to use FlexIO and the regular I/O pins... There's even master SPI sample code in the reference manual, you only need to change it slightly to output more bits in parallel.
You can implement QSPI using FlexIO. Specifically FlexIO2 has two sets of four consecutive lines available (0-3, 16-19) and supports interrupts, DMA and external triggers (XBAR from other modules).
The compiler is likely still optimizing them away, since they're const (and have to be, to go in PROGMEM). Maybe try doing something it can't optimize, like printing their starting/ending addresses?
CSINTERVAL might also play a part, especially if you're running the test code in a loop (although it's unclear if the hardware enforces it for every read or only consecutive reads/when necessary).
This is one of many...
Right, dsb should be at the end of irq_gpio6789() - I thought I'd checked before and it was, but I guess I imagined that.
(It's more efficient to have it in one place rather than relying on every custom gpio handler...
I thought the multi-gpio ISR handler in teensyduino (it's called gpio6789 or similar) had a dsb instruction at the end of it to handle this, am I imagining that?
You do. It's not about cache usage, it's to ensure any instructions that clear hardware interrupt registers have actually completed (and clear the pending interrupt) before the CPU exits the interrupt routine. It's even...
You could just do it more or less the same as you were planning but configure the output pins for open drain operation. Instead of sending voltage, they would switch between being open circuit (LED off) and ground (LED...
Bus interrupt lines are usually active low, designed to be pulled down using open-drain drivers. If you did that they effectively wouldn't need ground return lines, and they're less prone to being triggered erroneously...
FlexIO with two timers - one ticking at double the clock rate (since shifting can only be done on a rising or falling edge) and the other generating the actual clock.
Shouldn't the line in red be comparing note to 0x7F instead of 0x3F? It's probably turning off the power (and the LED) at note 63, with the remaining messages already received but still waiting to be processed.
It looks like it might be being used in place of an empty string rather than NULL, so the correct replacement would be:
{ scale(s, ""); }
(Checking the argument against NULL is certainly not a bad thing though.)
Pin 1 is FlexPWM1 pin, you'd have to read the reference manual to find which registers hold the state of the outputs for that module (and if it's possible to trigger an interrupt when it changes).
Rather than using an existing hardware interrupt, the ARM CPU supports two software controlled exceptions.
First is the supervisor call (exception #11) triggered by the "SVC" instruction.
Second is PendSV (exception...
Also very possible, multithreading without an MMU to track stack usage can be quite a challenge...
Both possibilities still don't explain the initial failure outlined in the opening post (where the program crashes when...
The correct way to do that would be to statically allocate the stack space and use the correct thread creation functions.
I really doubt FreeRTOS isn't returning an error when it tries to create a new thread and...
I don't, not in the habit of buying a lot of cards and the first thing I do is zero the whole drive to make sure it's not fake / clear out any manufacturer's garbage.
But I can tell you an easy way to end up with a...
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