forbiddenera
Well-known member
Hi,
I was thinking of trying to use a T4.1 to try and emulate an old-school eeprom, at least just the read side, such as a 27c256/27c512
There are 15-16 address pins and 8 data pins. The address requested is asserted on the address pins and then the data is set on the output pins.
Timing is obviously important in this application. I'm not sure it can be done, though in theory, the T4.1 should be fast enough.
Doing research, it seems like this could possibly be done with the DMA/eDMA but I'm not sure where to begin..I have been reading around the manual and here a bit, so I have a general idea but..
The idea is to be able to manipulate the memory in real-time from some externally connected host. The T4.1 could boot up, read a 256kbit chunk from flash, sdcard or something into memory. That memory could be modified in real time, say over a serial connection from a PC host.
The idea is to then setup the DMA/eDMA to read the 15-16 address pins into some memory/variable, then use that to decide what byte of our in-memory chunk to put on the 8 output pins.
Some timings from the datasheet (sst27sf256/sst27sf512) for the 70ns variant (also shows 90ns chips, though, in our application we try to use 70ns ones for reliability, the actual target mcu is usually running ~10mhz)
tRC = read cycle time = minimum 70ns
tCE = chip enable access time = maximum 70ns (our target leaves the chip always enabled)
tAA = address access time = maximum 70ns
tOE = output enable access time = max 35ns (our target does seems to use this)
tOLZ = OE# low to active output = min 0 ns (no max)
tOHZ = OE# high to high-z output = max 25ns
From the timing chart tAA is the time from address pins being set to data being valid on data pins, tRC looks like the minimum amount of time the address pins need to be set for a read cycle.
So basically I need to read 15-16 bits from 15-16 address pins, use those bits as an offset for somewhere in memory where my output data lies to output the byte there to the output pins, rather quickly.
If I'm correct, I should be able to read input pins directly from memory with some perhaps even being contiguous? Thusly, I'd want to setup a DMA transfer to read say 16 bits/2bytes from whatever address is used for those pins state and write it out to some other address (if that's even needed? maybe as a buffer?) where it can be used as an offset for a pointer to the data for a second DMA transfer to the output pins?
I was also considering using a shift register to reduce the number of physical output pins I need, but I don't think a 595 will be just quite fast enough, maybe - but that would be another option, pushing the data out serially.
3500 pages sucks
I was thinking of trying to use a T4.1 to try and emulate an old-school eeprom, at least just the read side, such as a 27c256/27c512
There are 15-16 address pins and 8 data pins. The address requested is asserted on the address pins and then the data is set on the output pins.
Timing is obviously important in this application. I'm not sure it can be done, though in theory, the T4.1 should be fast enough.
Doing research, it seems like this could possibly be done with the DMA/eDMA but I'm not sure where to begin..I have been reading around the manual and here a bit, so I have a general idea but..
The idea is to be able to manipulate the memory in real-time from some externally connected host. The T4.1 could boot up, read a 256kbit chunk from flash, sdcard or something into memory. That memory could be modified in real time, say over a serial connection from a PC host.
The idea is to then setup the DMA/eDMA to read the 15-16 address pins into some memory/variable, then use that to decide what byte of our in-memory chunk to put on the 8 output pins.
Some timings from the datasheet (sst27sf256/sst27sf512) for the 70ns variant (also shows 90ns chips, though, in our application we try to use 70ns ones for reliability, the actual target mcu is usually running ~10mhz)
tRC = read cycle time = minimum 70ns
tCE = chip enable access time = maximum 70ns (our target leaves the chip always enabled)
tAA = address access time = maximum 70ns
tOE = output enable access time = max 35ns (our target does seems to use this)
tOLZ = OE# low to active output = min 0 ns (no max)
tOHZ = OE# high to high-z output = max 25ns
From the timing chart tAA is the time from address pins being set to data being valid on data pins, tRC looks like the minimum amount of time the address pins need to be set for a read cycle.
So basically I need to read 15-16 bits from 15-16 address pins, use those bits as an offset for somewhere in memory where my output data lies to output the byte there to the output pins, rather quickly.
If I'm correct, I should be able to read input pins directly from memory with some perhaps even being contiguous? Thusly, I'd want to setup a DMA transfer to read say 16 bits/2bytes from whatever address is used for those pins state and write it out to some other address (if that's even needed? maybe as a buffer?) where it can be used as an offset for a pointer to the data for a second DMA transfer to the output pins?
I was also considering using a shift register to reduce the number of physical output pins I need, but I don't think a 595 will be just quite fast enough, maybe - but that would be another option, pushing the data out serially.
3500 pages sucks