@xxxajk so ideas 1-3 are pretty much the only way to make it work, even at these lower speeds (up to 20).
There are two issues:
1) the main DMA is a just a single controller. it has multiple...
Type: Posts; User: miciwan
@xxxajk so ideas 1-3 are pretty much the only way to make it work, even at these lower speeds (up to 20).
There are two issues:
1) the main DMA is a just a single controller. it has multiple...
The input clock is less of a problem then actually getting the data out. You can overclock FlexIO (though when it's too high compared to other frequencies, it starts to misbehave, like Razo mentions...
Oh, BTW (just to derail everything further), Paul, one thing that I noticed while looking into all this: startup.c clears the entire AHBCR register for FLEXSPI2, here:
...
FWIW I dug it out in the docs. I won't have a chance to try it out today, but for reference:
https://www.nxp.com/docs/en/application-note/AN12437.pdf is a really good application note with details...
Thanks for the answer Paul.
I believe the reason I'm not really seeing much of a difference when playing with priorities is related to that second question. While all the DMA machinery is doing...
Ok, maybe slightly different (somewhat related though) question :)
Does anyone know if there's any control over arbitration of access to EXTMEM? For example, IOMUX has the bits in IOMUXC_GPR_GPR2...
Does anyone have any practical experience with DMA, priorities and preemption on Teensy 4/4.1?
I have a process that reads out FlexIO shift registers with a DMA into a larger buffer(s) in local...
It will need to refilled every 32 bytes.
On each shift 8 bytes are shifted and the top bits are filled from a previous shifter (assuming the setup on the picture). The entire set is going to be...
Oh, I just noticed that the transfer callbacks are only called on non-active/finished transfers from the endpoint's list - so technically it's not possible to overwrite an in-flight transfer - which...
Trying to debug it more, though it's pretty annoying without any serial communication... anyway, I switched to using multiple transfer descriptors and buffers, to ensure I'm not overwriting any...
Hi,
I'm trying to implement USB Video Class on Teensy 4.1 to stream video feed from the camera attached to my Teensy. Setup of all the descriptors was fairly painless, and the device quickly...
The comment about 10MHz was about doing DMA from GPIO pins. There, you're somewhat limited by the latency between the pin going high and the DMA request being generated/processed. With FlexIO, you...
Yeah, it totally helped. Connecting all the Teensy ground pins to the analyzer made it way better. I haven't done any test with a dedicated PCB yet.
Yup, they cannot generate DMA requests (or rather they most likely can, it's just not routed to the DMA Mux). With the interrupts I've been generally seeing some weird stuff going on. Enabling them...
Nice!
@easone do you happen to remember what problems you had when using the shifters 4-7? In my experiments, they were behaving just fine, but I haven't tested them really thoroughly. BTW, in...
The manual is indeed pretty inconsistent. Most of the sections just talk about SHIFTERi. The text description of the parallel interface in 50.3.4.1 mentions shifters 0-7, and so does the example...
Hi everyone,
I'm slowly working though different parts of the documentation, to build the enough understanding of the i.MX RT1060 to use it in one of my projects. Two important components will be...
Sure - just a signal analyzer hooked up straight to Teensy.
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But the ground was a good direction! Thanks for that tip! I did connect ground in few more places rather than only two, and it...
There's no PCB, it's just the logic analyzer/signal generator hooked up to Teensy pins. And the same thing happens at lower speeds too. With 12bit bus, I'm seeing these glitches even at 1MHz. And on...
Hi everyone,
I'm seeing some unwanted behavior and I was hoping that someone could advice on what it could be caused by and/or what could I do about it.
Long story short, I'm working on...
I tried doing similar setup for the output and it works fine too. I set up the FlexPWM module to ouput the clock signal on Teensy pin 4 (should be doable with QuadTimer too, but FlexPWM docs were...
@KurtE - ah, great points. Properly flushing/invalidating caches is crucial when working with such systems, thanks for pointing that out. TBH, with this being my first T4.1 thing that I touched, I...
I was going through the DMA related things recently, starting from scratch, and I was writing things up as I went through them. I posted the thing here:...
Hi everyone,
I have recently started looking into using some of the lower-level functionality of the Teensy 4.1/iMX RT 1060, including DMAs, register-level access to pins etc, and eventually...
Like I mentioned, my Vin just doesn't get to the on-board voltage regulator.
Teensy 3.2 is 4 layer board, right? I don't really know how it's routed, I don't know how deep my cut was compared to...
The image is mirrored for some reason, I just hooked up the microscope to my PC, I didn't bother with any setup.
Right now, none if this external circuitry is connected (but basically the USB...
Here's the picture of the cut, I did it along the whole pads.
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Is the trace connecting Vin to the voltage regulator anywhere there? I clearly must have damaged that somehow, and I'm not...
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Admin Edit:
If your Teensy 3.2 is bricked after cutting too deep, info & a solution can be found here:
...
Hmm, ok, I think i figured it out.
After a closer inspection of the board itself, it looks like two outputs of the microcontroller are shorted:
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and as it happens these are the two USB...
I tried doing all this without anything hooked up to any of the USB ports, after a fresh reboot etc. (no HID devices were active in the system).
I'm having the same problem, *but* on just plain Teensy 3.2, on Windows 10. Hooking up the board to the USB port gives me "USB device not recognized".
The cable that I'm using is a tested data...