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Type: Posts; User: andrea1984

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  1. Replies
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    I did all the possible combination of internal...

    I did all the possible combination of internal Teensy clock, unfortunaly there is the need of an oscillator that is a multiple of power of 2, like an 6.144 MHz, so that 307.2kbps is an integer...
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    The reason is that I have to work at 307.2 kbps,...

    The reason is that I have to work at 307.2 kbps, and I found that is only possible with certain oscillators, that I can change on mcp2515 board
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    Can I use this library with my Teensy 4 and...

    Can I use this library with my Teensy 4 and MCP2515 board through the SPI interface?
    I need to use the MCP2515 board.
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    There is no need to shift 0, the currByte value...

    There is no need to shift 0, the currByte value is initialized to 0.
    I've disabled the interrupt on CLK line, but CS (gate) interrupt maybe is needed; I can try reading the CS pin too in the while...
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    I've a Zynq that generate the data, using the ARM...

    I've a Zynq that generate the data, using the ARM CPU and the FPGA core.
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    Is it working with Teensy 4 too?

    Is it working with Teensy 4 too?
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    Setting the Teensy CPU to 600MHz, it lost the...

    Setting the Teensy CPU to 600MHz, it lost the first bit of the stream.
    With idxBit = 1, the data stream is correct unless the first bit.
    I think the attachInterrupt routine is not fast as the clock...
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    With your hint I successfully tested this bus at...

    With your hint I successfully tested this bus at 6MHz, but only setting the Teensy CPU at 912MHz (overclocked).

    This my new code:




    const int ledPin = 13;
    const int dataPin = 0;
    const...
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    With 1.5 MHz of clock on master, I can receive...

    With 1.5 MHz of clock on master, I can receive all data correctly with my original code and the @defragster modification; if I use a clock of 3 MHz, the received data is not valid anymore.
    I think...
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    When the master want to send data puts CS high...

    When the master want to send data puts CS high (Gate), when it finish put CS low. It's a one direction communication.
    Is not a SPI, but it has something in common. In this scenario the Teensy should...
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    Sorry for my bad english. SPI works with shift...

    Sorry for my bad english.
    SPI works with shift registers, so if I want to read a stream of 35000 bytes from a peripheral like I want, I've to send 8 (or 16) bytes from the master to the slave and...
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    Because I cannot choose the protocol. Even it...

    Because I cannot choose the protocol. Even it seems a SPI, there is not answer to the data (like SPI has, with the same data length).
    It is a one direction stream data at 6Mhz, and the packet has...
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    I've an oscilloscope monitoring the 3 lines, and...

    I've an oscilloscope monitoring the 3 lines, and all the data is noisy (compared to 100 kHz), but with the correct timing. I'll attach a photo tomorrow.



    I'll try this trick


    In the final...
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    Maximum interrupt speed on Teensy 4

    Hello,
    I've a custom protocol (similar to SPI) to decode, made with 3 lines:
    - ENABLE, High when data is valid
    - CLOCK, at 6 Mhz
    - DATA

    I've attached 2 interrupts on ENABLE and CLOCK input,...
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    I tried with all 3 possible clock sources and all...

    I tried with all 3 possible clock sources and all 64 dividers, I can't reach the speed with an error below 300.
    The unusual speed I think is related to the usage of power of 2 oscillators, like...
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    I've to use CAN 2.0. Have I use a specific...

    I've to use CAN 2.0.
    Have I use a specific clock? How can the 307200 speed pass the bestError limits (492 bestError achieved is more than 300 admitted) on setBaudRate function with a clock of 24MHz...
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    Hello, I need to set the speed of CANBus at an...

    Hello,
    I need to set the speed of CANBus at an unusual speed of 307.2kbps.
    How can I make this possible? I didn't try (because I don't have the Teensy 4 yet), but reading the library source code...
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