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Alright! This will be useful for profiling code sections. I have some concerns with regard to execution speed with an isr inside something I'm working on, this looks like a way to check it out.
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OK, based on the register in question I'd been wondering why it was updating just every microsecond,. But I see that isn't the case at all. Good to know when using it to convert to time.

Does it...

Thanks for the tidbit, @defragster. I wasn't aware of ARM_DWT_CYCCNT.

I noticed some peculiar variations in the benchmark results that were resolved by using micros() instead of millis() to get the execution time (along with a few minor code changes to account for the...

BTW, the version writing to SET and CLEAR runs slower is because it uses two writes to the GPIO register, compared to one that writes to TOGGLE. So the benchmark results are consistent with this.

I modified my code to benchmark all three approaches and it reports a different result when modifying the TOGGLE register. I'm not sure why -- I didn't change the code other than rename the various...

Writing to the TOGGLE register benchmarks between the versions that modify DR and SET/CLEAR , somewhere around 80MBytes/second. Writing to SET/CLEAR is a bit more than twice as fast, according to my...

RE: the toggle register -- good idea! that would take care of the precedence issue. It actually will be more like my original approach, but would use a different register. So it should be a...

Benchmarking my routines gave me a read rate a bit over 70MBytes/second and about half that for writes. Quite a bit slower than I had expected for writing. Delving into the digitalWriteFast code I...

I should add that el_supremo must have seen the un-edited version of my first post (I caught the error before he posted his comment). So latecomers won't see my error.....I think....

Maybe it's...

Yes, good catch. Some additional experiments have shown that the bitmask isn't needed at all.

For various reasons I've been looking at various ways to get reasonably fast parallel I/O for 8 bits on a teensy 4.0. None of the T4.0's GPIOs that are used for digital I/O have 8 contiguous bits,...

Another approach would be to use the CPU, but use an interrupt routine to perform the bit-bang. One of the spare timers could generate an interrupt every 250ns to output the next bit in your serial...

Thanks to all for the input.

I loaded lubuntu-18.04LTS on the old laptop. I believe it's the last "lightweight" 32-bit Ubuntu distro. Arduino and Teensyduino appear to run OK, but the old laptop...

The problem is that Teensy.exe requires a library that's not present -- libgtk-3.so.0. When called, it quietly exits so it wasn't immediately obvious what was going on.

Unfortunately, this...

Editing platform.txt found in arduino-system-follder/hardware/teensy/avr to eliminate calls to teensy_secure got rid of the error messages relating to teensy_secure. So perhaps my missing library...

As long as teensy_secure has to run in order to compile Teensy code, I am in fact dead in the water. Regardless if it makes a lockable version or not, that utility apparently is called into action. ...

I recently installed copies of the most recent Arduino IDE (1.8.16) and Teensyduino 1.55 on a Dell D600 running Puppy Linux (it works pretty well on old computers). The combination _seems_ to work...

A resistor in the gate line also will help suppress oscillations that could occur when the device is switching. Regarding the sleep/hibernate question, if the digital pin becomes a high impedance...

SCK2, CS2, MOSI2 and MISO2 are available on the back of the T4.0. They are pins 37, 36, 35 and 34 respectively. Not real easy to use, being part of the SD card socket footprint. However, I have a...

That's an interesting idea. Examination of the reference manual indicates that there are 4 LPSPI blocks, and they can be individually configured as a Master or Slave. I'll have to look at the IOMUX...

The performance of a QSD-based SDR is highly dependent on the ADC. While the built-in ADC's sample rate is fast enough to permit decoding wideband FM, losing 4 bits (12 vs. 16) isn't something I...

Some online searching has indicated that the dual data mode for SPI transfers data on both the rising and falling edge of SCK. For instance, see...

Table 50-9 in the processor reference manual shows an example of a FlexIO setup configured as an SPI master. That would be a good starting point. It should be possible to allocate a third shifter...

Specifically, the 4 series. When you say "LPSPI chapter" are you referring to the data sheet?

I've been looking at fast dual ADC chips, with a possible SDR application for the I/Q channels. Most audio codecs run out of gas above 192KSPS (if you want to stick with the data sheet anyway) but...

Thank you for the information. I'll take a look at the info on github.

Mark

First post here. Owner of a Teensy 4.0, writing code with the Arduino IDE on Ubuntu 18.04.

I'm working on a couple of non-audio applications* that need 192KSPS@16 bits, which I believe eliminates...