can you setup a small example i can load to test?
Type: Posts; User: tonton81
can you setup a small example i can load to test?
Shouldn't you set the filter only after running begin()?
for ordered frames you need FIFO, otherwise you'll have to build your own frame re-assembly code for multiframe (you can build both ways, but FIFO would make the rebuilding easier, also remove...
Yeah, that would require defining CAN2, CAN3, asserts should work as is:
typedef enum CAN_DEV_TABLE {
#if defined(__IMXRT1062__)
CAN0 = (uint32_t)0x0, <------------- This was added to...
You can try this?
23429
added checks:
#if defined(__MK20DX256__) || defined(__MK64FX512__)
static_assert(_bus == CAN0, "Only CAN0 works on Teensy 3.2/3.5");
Indeed, it compiled in the arduino IDE as well I see, I just don't wanna add much code bloat. Going ahead after compilation should result in undefined behaviour though should the wrong one be used. I...
for the define, thats just a pointer, _CAN1 wont compile on T3.2 anyways
FIFO allows ordered receptions, mailboxes can receive in any order as long as a slot is empty. you can have FIFO and...
Can you try this patch? Originally it only supported 31 mailboxes max, as Teensy 3.x had 16 mailboxes, bit 31 was used for the global handler. Now it should support up to 64 mailboxes with a general...
sorry i dont understand how that works, but maybe i can look at how Collin did it and see if i can port it over
just add this to your library after including flexcan header:
void ext_output1(const CAN_message_t &msg) {
//do whatever with message
}
and enable MB/FIFO interrupts in setup, the...
are you on the latest github version? if not try that out
dont set filters BEFORE calling enableFIFO
and by the way.....
msg.id == 0x18DAF111 & msg.buf[1] == 0x41 & msg.buf[2]
& is not && :)
only pitfall may be the SD latency if any. What most people do is fill a 512 buffer in ram then write that to SD while you continue logging to a different 512 buffer. You can do this with a standard...
remove EXT from setMBFilter (that function doesn't use that), remove events() from loop, and you enabled FIFO last in setup, which makes your filters not effective, also MB7 is a TX mailbox, so that...
what is slow? reception? transmission? code responses? how does the loop() code look like? are you using events()? if using events(), there may be a delay somewhere in your code before the queue can...
You can have up to 8 FIFO filters (0-7) by default, 8 more after sacrificing 2 mailboxes (0-15), which would leave you with 6 TX mailboxes instead of default 8. It's a bit complex but highly...
if you enable FIFO, you dont have any reception mailboxes, only 8 TX mailboxes MB8-MB15. Because you are using FIFO without mailboxes you should use setFIFOFilter(0, 0x18DAF111,EXT)... 0 for 1st fifo...
read my post above
EXT is used for setMB(), optional parameters in setMBFilter are for multiple IDs only
mailboxStatus() will display MB1 as a STD mailbox. use MB4 for extended receptions.
remove the condition checks to make sure you see the frame first, usually print it out, easier to debug. also remove filtering until you get the expected output, then you may filter frames as needed...
no, it's pulled in manually by paul, i think its because i dont have a library config file or have it on Library manager
thats cool, but thats 24 TX mailboxes when seq is only using 1 in FIFO mode, I think the higher queues and interrupt helped with ordered transfers
sounds like a timing issue, try adding a delay in setup somewhere before begin() is called
try to use a different pin, like the original SPI bus pin 10, you shouldn't need to change pins for it to work
why adc? are you sharing the bus? is it releasing the MISO line? I don't know your connections, everything you attached, or code, just bits of pieces and alot of guesswork...
sounds like you have...
if you have a problem at reading then yeah, that won't make my library work as it needs to read the registers. make sure your SPI MISO and MOSI lines are correct, theres an SPI connection issue...
well it should work with demo above, i have 8 chips running on a T4.0 on SPI with pin 10 as CS
if it's wired and configured properly, mcp.info() will detect it
what SPI pins you using?
example in first post, constructor is using 10 for CS, you would use 37
1 2 3 4 5 6 7 8
push front 9 will become:
9 1 2 3 4 5 6 7 8
push back 6 will become:
9 1 2 3 4 5 6 7 8 6
pop front returns 9, your data becomes:
1 2 3 4 5 6 7 8 6
pop back returns 6, your...
I needed BLE support for my Teensy 4.0 project, rather than deal with 2 mcus i added CANbus support TO ESP32 and have teensy use CAN to control the BLE devices programmed on the ESP32
pushing back puts your data at the end. popping front pulls data from the front (oldest)
this is why you can do FIFO/LIFO
odd.... it is the identical chip in both
are you sure theres no extra code blocking thats making the time expire sooner before feeding? (maybe something is taking a long time to initialize?)
if the callback doesnt fire without events(), you are not using the latest github copy. Please update.
Also increase your TX_SIZE in the constructor, the queue may be overflowing while waiting...
you can either use the .seq flag to enable sequential on absolute first TX mailbox, or just setup only 1 TX mailbox. you can have up to 64 on T4, 16 on T3, and if you really wanted you can setup 1TX...
Note alot of google results show issue with your transceiver. I am using all 3 CAN busses in my project. One of the issues explained in that post is that transceiver being able to receive but not...
Also you may wanna look at the first post here:
https://forum.pjrc.com/threads/51870-Help-getting-Canbus-data-from-teensy-3-2-and-SN65HVD230-transciever!
i agree, reception of fifo is ordered 6 deep, however on transmit, any of the 8 remaining TX mailboxes can send in any order. Sequential will use only the absolute first TX mailbox when sending...
toggle a led in your loop() to make sure the loop() is still running, also check your CAN lines are terminated
can you try a different tranceiver? I've blasted 1Kbyte arrays with TeensyCAN with CRC validation, if frames were missing it,ll never reconstruct the array at other node, pass the CRC, and fire a...
did you try changing the clock? all teensy flexcan libraries (can2.0) use the same calculation script, try it with different clocks (setClock()) and try your baudrates with the new clock.
teensy...
you mean like 33,333 and 10? it works but all nodes must match
the background handler runs in parallel with the interrupt callback (with or without events(events is for sketch callback which uses queues))
so just removing events() will make your own callback...
are you having issues transmitting or receiving the lost frames? you can play with the queues in constructor to find out?
Try using setClock() to configure the controller to use 60MHz peripheral...
you can try setClock() method, older teensies ran at 16mhz osc clock i believe, t4 runs at 24mhz osc by default, you can go up to 60MHz peripheral clock if needed. I am using 60MHz accross 3 busses,...
could it be possible the dynamic memory allocation "new" being called in the loop in multiple functions (also within a for loop) may be eating up the ram? have you checked if the heap is decreasing?
maybe the lcd code is slowing things down?, also if can.events() is in the loop(), remove it. The callback will fire directly rather than use the queues.
i guess there is 3 modes to flexcan_t4,...
On Teensy 3.2/3.5, you have CAN0
On Teensy 3.6, you have CAN0 and CAN1
on Teensy 4.0/4.1, you have CAN1,CAN2, and CAN3.
It's based on the hardware layout names on the controller as per the RM....
try using the FlexCAN_T4 example, and put in the constructor CAN0 since you are using teensy 3.5. See if anything changes, it is more recent than IFCT
Also you will miss frames if your loop is...
Tim, don't forget to check your Junk mail (spam pun intended) :P
the amount of mailboxes you have doesn't have anything to do with long messages, you would have to write a protocol that would take the received frames and reassemble them as theyre streaming, and...