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Type: Posts; User: markkimball

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    SCK2, CS2, MOSI2 and MISO2 are available on the...

    SCK2, CS2, MOSI2 and MISO2 are available on the back of the T4.0. They are pins 37, 36, 35 and 34 respectively. Not real easy to use, being part of the SD card socket footprint. However, I have a...
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    That's an interesting idea. Examination of the...

    That's an interesting idea. Examination of the reference manual indicates that there are 4 LPSPI blocks, and they can be individually configured as a Master or Slave. I'll have to look at the IOMUX...
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    The performance of a QSD-based SDR is highly...

    The performance of a QSD-based SDR is highly dependent on the ADC. While the built-in ADC's sample rate is fast enough to permit decoding wideband FM, losing 4 bits (12 vs. 16) isn't something I...
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    Some online searching has indicated that the dual...

    Some online searching has indicated that the dual data mode for SPI transfers data on both the rising and falling edge of SCK. For instance, see...
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    Table 50-9 in the processor reference manual...

    Table 50-9 in the processor reference manual shows an example of a FlexIO setup configured as an SPI master. That would be a good starting point. It should be possible to allocate a third shifter...
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    Specifically, the 4 series. When you say "LPSPI...

    Specifically, the 4 series. When you say "LPSPI chapter" are you referring to the data sheet?
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    SPI variant question

    I've been looking at fast dual ADC chips, with a possible SDR application for the I/Q channels. Most audio codecs run out of gas above 192KSPS (if you want to stick with the data sheet anyway) but...
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