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  1. I also wondered what peripherals might be already...

    I also wondered what peripherals might be already in use. I don't have any knowledge - perhaps one of the experts will point you in the right direction.

    Attached is some commented code on using...
  2. @JBeale - You might find Beta Tests post #3578...

    @JBeale - You might find Beta Tests post #3578 and #3586 interesting. These refer to making the 150 MHz peripheral clock available for GPT2, which has a 32 bit counter.

    I worried about making...
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    Thanks for your useful response. I have just been...

    Thanks for your useful response. I have just been doing some more experiments with T4 and have further very good results which may be of interest. Appreciate that temperature is a key factor - and...
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    T4 and Peripheral Clock adjustments

    When measuring the output frequency of a QTIMER on a T4, I found it to be 5ppm slow on the theoretical value. This will be attributable to the 24 MHz oscillator also being 5ppm slow (within spec and...
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    I believe the keyword "volatile" provides some...

    I believe the keyword "volatile" provides some insurance. Against what? The compiler making assumptions that differ from my own.

    What is an ISR? Some code that might happen - but your'e never...
  6. So, in summary, the C code modulo operation "A %...

    So, in summary, the C code modulo operation "A % B" is realised by two assembler instructions - "sdiv" (signed division) followed by "mls" (multiply and subtract). Sdiv finds the integer result R of...
  7. Two excellent replies... thankyou both. The...

    Two excellent replies... thankyou both.

    The "Compiler Explorer" is a whizz tool. Not seen it before.
  8. Modulo division - how does it work?

    Does anyone know how the algorithm works for performing modulo division in the Arduino/Teensyduino IDE?

    I'm interested to know if the timing for this operation might depend on the size of the...
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    I forgot to add that in order to get the 81 KHz...

    I forgot to add that in order to get the 81 KHz frequency exact with Scheme (3), I needed to change the value from 0x04 to 0x08 for one of the digital capacitors...



    //This following code...
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    So the Scheme (3) with absolute timing is as...

    So the Scheme (3) with absolute timing is as follows, recalling that MODA is 6 nS early, and MODB is 10 nS late:

    MODA (-6nS), MODB (+4nS), MODA(-2nS), MODA(-8nS), MODB (+2nS), MODA (-4nS), MODA...
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    Having found a solution which was an almost...

    Having found a solution which was an almost perfect 81 KHz frequency square waveform, I wondered if it was now possible to reduce the jitter without loss of frequency precision.

    The jitter is...
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    Eighty One KHz

    I had need recently to see if I could generate a very precise 81 KHz signal using a Teensy 3.5. I was looking for precision much better than 1 Hz.

    This frequency is employed by Radio Station GYN2,...
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    Glad to help. Yes, it does mean that the board is...

    Glad to help. Yes, it does mean that the board is OK to work with. You may wish to experiment with turning the LED on and off by writing your own code. You learn a great deal by such experiments.
    ...
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    The schematic for Teensy 3.2 can be found here......

    The schematic for Teensy 3.2 can be found here... https://www.pjrc.com/teensy/schematic.html

    As you can see on the right hand side of the diagram, there is nothing particularly special about the...
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    QTIMER INTERRUPTS from COMPARATORS

    @defragster - This three phase example illustrates the point. It is derived from my previous "alternating compare" example, which is why Compare1 and Compare2 are both being used.

    I have not set...
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    QTIMER INTERRUPTS from COMPARATORS

    With QTimers, there are two "Status and Control" registers - for example, TMR3_SCTRL1 and TMR3_CSCTRL1. The first is the Status/Control for the timer as a whole. The second is the Status/Control for...
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    Qtimer

    Been playing around again tonight with QTimers. Interesting idea of using QT3 in quadrature - employing QT3_Timer0 on pin 19 and QT3_Timer1 on pin 18.

    This example also uses the "Alternating...
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    Yes - I should use the symbols - even just to...

    Yes - I should use the symbols - even just to find any errors that might have crept in. I do find it educational, though, going through the registers bit by bit - it sticks in the brain better with...
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    Not studied yet but there is a QUADRATURE option....

    Not studied yet but there is a QUADRATURE option. One of the control bits can also invert.

    I did get a QUAD output from GPT2 as well. Set Compare1 for frequency, then Compare2 and Compare3 can be...
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    Gentlemen - Thankyou both. I could have stared at...

    Gentlemen - Thankyou both. I could have stared at those ISR lines for days and not spotted it. So many other places where you write a '1' to clear a flag (familiarity breeds contempt). And the manual...
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    Qtimer

    I have run into T4 trouble while experimenting with a QTIMER QT3_0. I am making an assumption that QT3_0 is free to use?

    I am using the QTIMER as a simple upcounter from 0 to COMPARE1 and then...
  22. Seems that Post #2 is the situation.

    Seems that Post #2 is the situation.
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    A Teensy from 1969

    With this week being the 50th anniversary of the Moon Landings, I thought I would share a picture of the "Teensy" I was using that same year. It was just over 12 inches long and 2 inches wide. But...
  24. Bare Bones Sketch

    Let the board cool down. Remove any SD Card or other attachments. Then attach to the USB socket and try running the attached "Bare Bones" sketch on your T3.6.

    It will flash the LED four times...
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    Re post #3691 on GPT2 Compare behaviour, once the...

    Re post #3691 on GPT2 Compare behaviour, once the "penny" has dropped, then the design implemented becomes much more comprehensible.

    The three Compare channels are not completely independant in...
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    Thankyou for your diligence, and well spotted on...

    Thankyou for your diligence, and well spotted on the comment 51.1.1 and 51.1.2. I had missed that.

    Looks like you are correct - it is a "feature". On the diagram of Fig 51-1, it too shows a line...
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    Here is a sketch which illustrates the quirky...

    Here is a sketch which illustrates the quirky behaviour of GPT2 Compare3 and Compare2.

    Notice that it is only GPT2_OCR1 that determines the period/frequency of the output sq wave on a scope.
    ...
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    ... And by the way, the value you need to put...

    ... And by the way, the value you need to put into "Compare 3" OCR3 or "Compare 2" OCR2 to get the square wave appear must be less than or equal to the value that you put into "Compare 1" OCR1. You...
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    Update on Red Alert #3662...

    I have done a lot of tests today. There is something VERY ODD about GPT2. I think its a design fault in the chip itself (either that or I am not understanding the way it is supposed to work).

    I...
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    Thanks for the tip. I will try that. The...

    Thanks for the tip. I will try that.

    The reason I'm suspicious that something has changed is that I have - so far - been unable to "go backwards" and undo the mux that switched on the 150 MHz....
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    Red alert !!

    I have suspicions tonight that my experiments with turning on 150 MHz for GPT timers may have damaged the chip internally. Until I can clarify this further, please will all beta users refrain from...
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    @Manitou - Tried "DSB" and it made no difference....

    @Manitou - Tried "DSB" and it made no difference. If I can summarize, using GPT2 it looks like this... If you only enable Compare2 using "GPT2_IR = 0x00000002;" then it ONLY WORKS (the ISR) if you...
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    I have not used "DSB", but will give it a try....

    I have not used "DSB", but will give it a try. Thanks for your reference - useful to see how someone else does it.

    I think the Compare1, 2 and 3 are completely independant of each other in their...
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    GPT Timer Interrupt Behaviour

    Interesting experience whilst experimenting with GPT1 and GPT2 today. Using the 150 MHz clock, I wrote a simple test to use GPT1 Compare1 to generate an interrupt every second. In the ISR, I reset...
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    GPT timer clock selections

    @manitou - Yup, the RTC looks to be that little tin at the side of the reset button. Cute. I was mentally expecting a round long tin for RTC. Habits...

    The reason for lack of option 5 on GPT_CR...
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    150 MHz now available for GPT's

    Success now with 150 MHz peripheral clock available to GPT1 and GPT2, using bit 6 = 0 for CCM_CSCMR1[PRECLK_CLK_SEL]. I gated/stopped both GPT2 clocks CG13, CG12 of CCM_CCGR0, also GPT1 clocks...
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    Well, I've had one attempt to go for it... not...

    Well, I've had one attempt to go for it... not succeeded yet. May take a little to figure out why not. I discovered that clock gating registers can upset the IDE and monitor, but managed to recover...
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    @Paul - I'm still nervous about changing bit 6...

    @Paul - I'm still nervous about changing bit 6 which is CSCMR1[PERCLK_CLK_SEL]. I can disable the PIT module with MDIS and set GPTn_CR control modules to zero, but I'm concerned that other modules...
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    Playing with GPT1 and GPT2, I found that the...

    Playing with GPT1 and GPT2, I found that the highest clock speed available in the Clock selections (powerup de facto) to be 24 MHz. I'm trying to make 150 MHz available for counting. Reading the 1060...
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    @mjs513 - Thanks, it all helps. XBAR is a new...

    @mjs513 - Thanks, it all helps. XBAR is a new area for me.

    Just reading the 1060 RM XBAR chapters, there is an intriguing statement 60.2.1 that "...any input (typically FROM external GPIO pin or...
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    Thanks both for assistance and patience with my...

    Thanks both for assistance and patience with my dumbness. That IOMUX chapter is cavenous. Big change from the T3 world on muxing. Example sketches with plenty comment lines are going to be essential...
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    So many Timers, its a job knowing where to start....

    So many Timers, its a job knowing where to start. I'll experiment with them all and probe the features. Maybe make a writeup later to help T4 newcomers like myself.

    I notice that GPT are 32 bits...
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    Just received a T4 Beta2. Can someone please...

    Just received a T4 Beta2. Can someone please point me at a post for the latest beta2 external pin ALT mappings? Thanks - not easy trawling through 141 pages of posts. (Imagine these pins will be in...
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    24 Mhz Osc Control

    I have scanned through the 1050 ref manual, but cannot see any "digital capacitors" to adjust/nudge ppm of the 24 MHz Osc frequency. Does anyone know different? The Osc diagram shows external...
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    Just performed another test string longhand... ...

    Just performed another test string longhand...


    unsigned char TestData1[] = {0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38};

    The paper answer in 14 bit binary was "01 1010 0010 0010". Expressed as...
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    I'm finding the 7 bit and 14 bit worlds very...

    I'm finding the 7 bit and 14 bit worlds very cranky. Suddenly realised why I can't see any patterns in my Loran data... the Eurofix message structure is out of placement sync with the data when...
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    Does "augmented" mean that you simply place the...

    Does "augmented" mean that you simply place the CRC first, before the message, when doing a longhand division by the polynomial (at the receiver)? Would you also agree that the "To compensate..."...
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    I notice that your printed CRC14's have some...

    I notice that your printed CRC14's have some values in excess of 14 bits. That cannot be right for a CRC based on 14 bit calculations? Methinks, the CRC cannot be a remainder if it is bigger than 14...
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    Timing of FastCRC... on my scope, it took 3.4...

    Timing of FastCRC... on my scope, it took 3.4 uSec to perform the CRC14.eloran call plus one DigitalWriteFast statement. That's a T3.5 running @180 MHz (and a very precise 180 MHz I might add, since...
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    Frank, Pete Using a T3.5, I made a test of...

    Frank, Pete

    Using a T3.5, I made a test of CRC14.eloran just now and it worked brilliantly. The 56 bit test data was... uint8_t buf[] = {0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA}; and this gave the...
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