I want to supply the Teensy just with the studio Master Clock (96kHz in our case) and have it generate it's own I2S LRCLK and BCLK (and MCLK if possible) from it. I've read through the whole iMXRT Reference Manual but it doesn't seem to cover this particular case, though I suspect it is possible given how powerful the processor is.
I'm anticipating that the Master clock input will use the LRCLK2 pin as an input and then the whole of SAI1 will slave to this with LRCLK1, BCLK1 and MCLK1 being outputs to drive the ADCs and DACs. BCLK2 would be unused as we don't distribute a high frequency clock around the studio. Ideally SPDIF-Out would also be synchronised to the Master Clock but not essential as we can source the SPDIF-in with the “Zero Bit Digital Black” output from the Master Clock generator.
Can anybody give me any hints on the clock routing and dividers I would need to do this ?
Many thanks
I'm anticipating that the Master clock input will use the LRCLK2 pin as an input and then the whole of SAI1 will slave to this with LRCLK1, BCLK1 and MCLK1 being outputs to drive the ADCs and DACs. BCLK2 would be unused as we don't distribute a high frequency clock around the studio. Ideally SPDIF-Out would also be synchronised to the Master Clock but not essential as we can source the SPDIF-in with the “Zero Bit Digital Black” output from the Master Clock generator.
Can anybody give me any hints on the clock routing and dividers I would need to do this ?
Many thanks