Not sure if it's a mistake but in the first page CAN3 is listed as:
so on pins 30 and 31, and as per that list, and the datasheet, EMC_36 and EMC_37 are the CAN3 FD pins
However when I looked into the core I see differently:
I think when you swapped the physical pins you forgot to edit those entries to reflect that
Already tested FlexCAN_T4 on B2 and it works on pins 0 and 1 (CAN2) and 22 and 23 (CAN1), but I think this is where Mike got stuck on FD, the registers wern't matching the physical pins
Also the CANFD daisy chain register seems to be missing, if i calculated the offset right, is this correct?
#define IOMUXC_FLEXCAN3_RX_SELECT_INPUT (IMXRT_IOMUXC_b.offset38C)
datasheet lists it as address 0x401F878C
the base of IMXRT_IOMUXC_b is 0x401F8400
so an offset of 38C should add up if im doing it right![Stick out tongue :p :p](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)
Code:
30 EMC_37 3.23 GPT1_3 3_RX 3:MCLK I-23
31 EMC_36 3.22 GPT1_2 3_TX 3:TX_DATA I-22
so on pins 30 and 31, and as per that list, and the datasheet, EMC_36 and EMC_37 are the CAN3 FD pins
However when I looked into the core I see differently:
Code:
#define CORE_PIN30_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24
#define CORE_PIN31_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23
#define CORE_PIN30_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24
#define CORE_PIN31_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23
I think when you swapped the physical pins you forgot to edit those entries to reflect that
Already tested FlexCAN_T4 on B2 and it works on pins 0 and 1 (CAN2) and 22 and 23 (CAN1), but I think this is where Mike got stuck on FD, the registers wern't matching the physical pins
Also the CANFD daisy chain register seems to be missing, if i calculated the offset right, is this correct?
#define IOMUXC_FLEXCAN3_RX_SELECT_INPUT (IMXRT_IOMUXC_b.offset38C)
datasheet lists it as address 0x401F878C
the base of IMXRT_IOMUXC_b is 0x401F8400
so an offset of 38C should add up if im doing it right
Last edited: