Constantin
Well-known member
I am now moving ahead with going into the programming of a power monitor based on the Teensy 3.0. Before I proceed further, I have a couple of questions...
Because Analogread is likely to slow for my application, I am thinking of dropping down into the actual ADC registers, just as I had on the Arduino version of the same meter. However, unlike the Arduino (328P-based) I can read differential inputs on the Teensy 3.0, so I will make use of them. I have an ADC driver chip from Analog Devices to provide the voltage signal (via transformer, step down resistors, and so on) as well as current signal coming out of a LTSR-6P current sensor as inputs. The VREF will be externally driven with a voltage source at 2.5V, which also serves as an input into the LTSR.
Looking over the ADC section in the manual, it appears that the best one can hope for (even in 16-bit differential mode) is approximately 13.8 bits ENOB. Which is fine for my applications, where even 12 bits differential would be pure happiness. A further look over the specifications suggests that the bus clock divisions are rather limited (1/2/4/8/16). My plan was to set the ADC clock divisor at 4 to enable 12MHz ADC clock operation.
My reading of the data sheet also suggests that the potentially quicker clock speeds for the ADC at lower bit rates (i.e. up to 18MHz @ 13 bit differential) are hard to realize unless a Alternate clock (ALTCLK) or Asynchronous Clock (ADACK) bits are set in the ADCx_CFG1 register. For whatever reason, there appears to be no discussion on how to program ADACK or ALTCLK in the reference manual we have on this site - the authors refer you to yet another manual. Anyone have the web addresses for these other manuals handy?
Since I cannot easily take advantage of the higher ADC clock speeds for sampling at 13 bits it would appear best to sample at 16 bits differential and then right shift the results by 2-3 bits since the difference in sample time would be negligible but the ENOB would presumably be higher?
Another point that I am a bit perplexed about is the ADHSC bit. When would it be set? The manual states "ADHSC should be used when the ADCLK exceeds the limit for ADHSC = 0." but the limits are not defined by sampling speed and clock rates other than for 13 bit and 16 bit differential operation. Assuming my ADC clock rate stays within the limits of the ADC spec (i.e. 2-12MHz for 16 bit diffy mode) can I safely leave the ADHSC bit at zero?
Many thanks for any guidance! Constantin
Because Analogread is likely to slow for my application, I am thinking of dropping down into the actual ADC registers, just as I had on the Arduino version of the same meter. However, unlike the Arduino (328P-based) I can read differential inputs on the Teensy 3.0, so I will make use of them. I have an ADC driver chip from Analog Devices to provide the voltage signal (via transformer, step down resistors, and so on) as well as current signal coming out of a LTSR-6P current sensor as inputs. The VREF will be externally driven with a voltage source at 2.5V, which also serves as an input into the LTSR.
Looking over the ADC section in the manual, it appears that the best one can hope for (even in 16-bit differential mode) is approximately 13.8 bits ENOB. Which is fine for my applications, where even 12 bits differential would be pure happiness. A further look over the specifications suggests that the bus clock divisions are rather limited (1/2/4/8/16). My plan was to set the ADC clock divisor at 4 to enable 12MHz ADC clock operation.
My reading of the data sheet also suggests that the potentially quicker clock speeds for the ADC at lower bit rates (i.e. up to 18MHz @ 13 bit differential) are hard to realize unless a Alternate clock (ALTCLK) or Asynchronous Clock (ADACK) bits are set in the ADCx_CFG1 register. For whatever reason, there appears to be no discussion on how to program ADACK or ALTCLK in the reference manual we have on this site - the authors refer you to yet another manual. Anyone have the web addresses for these other manuals handy?
Since I cannot easily take advantage of the higher ADC clock speeds for sampling at 13 bits it would appear best to sample at 16 bits differential and then right shift the results by 2-3 bits since the difference in sample time would be negligible but the ENOB would presumably be higher?
Another point that I am a bit perplexed about is the ADHSC bit. When would it be set? The manual states "ADHSC should be used when the ADCLK exceeds the limit for ADHSC = 0." but the limits are not defined by sampling speed and clock rates other than for 13 bit and 16 bit differential operation. Assuming my ADC clock rate stays within the limits of the ADC spec (i.e. 2-12MHz for 16 bit diffy mode) can I safely leave the ADHSC bit at zero?
Many thanks for any guidance! Constantin