ADC Guidance

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Constantin

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I am now moving ahead with going into the programming of a power monitor based on the Teensy 3.0. Before I proceed further, I have a couple of questions...

Because Analogread is likely to slow for my application, I am thinking of dropping down into the actual ADC registers, just as I had on the Arduino version of the same meter. However, unlike the Arduino (328P-based) I can read differential inputs on the Teensy 3.0, so I will make use of them. I have an ADC driver chip from Analog Devices to provide the voltage signal (via transformer, step down resistors, and so on) as well as current signal coming out of a LTSR-6P current sensor as inputs. The VREF will be externally driven with a voltage source at 2.5V, which also serves as an input into the LTSR.

Looking over the ADC section in the manual, it appears that the best one can hope for (even in 16-bit differential mode) is approximately 13.8 bits ENOB. Which is fine for my applications, where even 12 bits differential would be pure happiness. A further look over the specifications suggests that the bus clock divisions are rather limited (1/2/4/8/16). My plan was to set the ADC clock divisor at 4 to enable 12MHz ADC clock operation.

My reading of the data sheet also suggests that the potentially quicker clock speeds for the ADC at lower bit rates (i.e. up to 18MHz @ 13 bit differential) are hard to realize unless a Alternate clock (ALTCLK) or Asynchronous Clock (ADACK) bits are set in the ADCx_CFG1 register. For whatever reason, there appears to be no discussion on how to program ADACK or ALTCLK in the reference manual we have on this site - the authors refer you to yet another manual. Anyone have the web addresses for these other manuals handy?

Since I cannot easily take advantage of the higher ADC clock speeds for sampling at 13 bits it would appear best to sample at 16 bits differential and then right shift the results by 2-3 bits since the difference in sample time would be negligible but the ENOB would presumably be higher?

Another point that I am a bit perplexed about is the ADHSC bit. When would it be set? The manual states "ADHSC should be used when the ADCLK exceeds the limit for ADHSC = 0." but the limits are not defined by sampling speed and clock rates other than for 13 bit and 16 bit differential operation. Assuming my ADC clock rate stays within the limits of the ADC spec (i.e. 2-12MHz for 16 bit diffy mode) can I safely leave the ADHSC bit at zero?

Many thanks for any guidance! Constantin
 
If you are measuring AC line power, you can't need a sample rate of over 5 kHz -- that's already good for the 50th harmonic of a 50 Hz line. Best to work on ensuring you have a good LPF before the ADC.

Note that 13 bits is resolution, not accuracy -- your overall accuracy will be limited by the reference accuracy, transformer bandwidth, and offsets at lower signal levels.
 
For whatever reason, there appears to be no discussion on how to program ADACK or ALTCLK in the reference manual we have on this site - the authors refer you to yet another manual. Anyone have the web addresses for these other manuals handy?

I believe ALTCLK is documented in section 3.7.1.7 on page 98. See chapter 5 and the diagram on page 142 regarding OSCERCLK.

I have not tried using ADACK yet, but my understanding is it's generated within the ADC and not sync'd to any other clock.


Another point that I am a bit perplexed about is the ADHSC bit. When would it be set? The manual states "ADHSC should be used when the ADCLK exceeds the limit for ADHSC = 0." but the limits are not defined by sampling speed and clock rates other than for 13 bit and 16 bit differential operation. Assuming my ADC clock rate stays within the limits of the ADC spec (i.e. 2-12MHz for 16 bit diffy mode) can I safely leave the ADHSC bit at zero?

The AVR chip on Teensy 2.0 has a similar "high speed" mode, with basically no documentation.

In the 62 page electrical specs datasheet, there's footnote 4 on Table 23 on page 37 says "To use the maximum ADC conversion clock frequency, the ADHSC bit should be set and the ADLPC bit should be clear".

Footnote 5 says "For guidelines and examples of conversion rate calculation, download the ADC calculator tool"

http://cache.freescale.com/files/so...pp_software/converters/ADC_CALCULATOR_CNV.zip

It's Windows only, but maybe that can help where the datasheets lack specific info?
 
If you are measuring AC line power, you can't need a sample rate of over 5 kHz -- that's already good for the 50th harmonic of a 50 Hz line. Best to work on ensuring you have a good LPF before the ADC.

Note that 13 bits is resolution, not accuracy -- your overall accuracy will be limited by the reference accuracy, transformer bandwidth, and offsets at lower signal levels.

Absolutely true... but I'm looking at sampling a 60Hz signal on two channels which means per your calculation one would want something in the 12KHz range. On the Arduino, I managed to get into the 5ksps range (for both channels, i.e. 10ksps overall, switching back and forth), which is close to the maximum possible. But that was a CPU pretty much dedicated to sampling and only spitting the results over to another CPU every second based on a external signal.

One benefit of a fast sampling rate is a smaller the phase shift between the two signals. Then there are the other 'housekeeping' things that the teensy will be doing, like sending queries out via RS485, getting replies, writing results to SDHC once a second, etc.

I hope that I got the other details you mention right.... the LTSR looks like a very accurate current monitor and the 2.5V reference voltage is a AD1582BRTZ series - good for 0.08%. The series reference also feeds the ADC ref voltage. The LTSR output is run through a voltage divider (4k7 / 0.1%), for the DADP0 channel while the DADM0 channel is also coming out of a voltage divider of the reference input voltage (i.e. also a pair 4k7 0.1% resistors) which also feed into the common-mode voltage input of the AD8137 (see below).

On the voltage side, the input voltage is designed to be as high as 265V for a 230V-rated appliance. The output out of the transformer is a nominal 6VAC at 230V in though as unloaded as the thing is, I expect it to be closer to the 10.8VAC the manufacturer lists for unloaded conditions. Anyway, once you convert to Vpp vs VACrms, output voltages are quite high, so I used a couple of big resistors (10k) to step the thing down and then feed a AD8137YRZ op amp to produce a nice input into the Teensy ADC on the DAD3 diffy channel.

An alternate approach to the above would be to eschew the LTSR and use a revenue-grade current sensor from Current Magnetics and a AD8137 to turn its AC output into something that the ADC would be happy with. The linearity (0.1%) is similar to that of the LTSR and the total cost would be somewhat less (~$15 vs $23).

Thanks again for your suggestions and I hope the above is somewhat understandable. I'd appreciate any feedback you have. If it's not obvious, I'm a Mechie dabbling outside my normal area of expertise.
 
Thank you!

The AVR chip on Teensy 2.0 has a similar "high speed" mode, with basically no documentation.... Footnote 5 says "For guidelines and examples of conversion rate calculation, download the ADC calculator tool"

Bingo! Here are some additional hints for people to take as they wish... per the windows tool mentioned above (thank you Paul!) the best 16Bit operation is only realized at 10MHz or below. Thus, unless I figure out how to set the ALTCLK, I'd have to go with the bus clock / 8 divisor, for a 6MHz ADC clock since 12MHz may be allowed elsewhere in the datasheet but is likely too quick for realizing the ENOBs promised in the data sheet.

FWIW, the tool recommends using the ADHSC bit whenever the ADC is running above 8MHz. This seems particularly important when sampling at lower bit rates (i.e. 13 bit diffy can be done at up to 18MHz per the data sheet). A 12MHz sampling rate for 12 bit diffy (which should be 13 IMO, but I am happy to be wrong) results in a sampling time of 3.22x10^-6s per sample or about 300ksps without resorting to continuous sampling mode.

So... for a 6MHz ADC clock, per the tool I'd be looking at 6.771x10-6s for every 16 bit differential sample or about 146ksps.... 10x more than I need. So, no need to delve into ALTCLK or other means of deriving a new ADC clock, 6MHz is more than fast enough.
 
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