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# Thread: How low is low enough?

1. ## How low is low enough?

So we recently had a discussion regarding the time it takes for the ADC to charge it's caps and produce usable results.

My question to you is: how low is low enough re: impedance? Is there a section in the manual that deals with the impedance vs sampling speed vs resolution? I didn't see it in the ADC section but I'm happy to educate myself. Just need to know where to look...

Background: using the teensy 3.0 adc with its default input range from 0-3.3v with a ltsr-np current sensor that has a 0-5v output. I was thinking of just using a simple 1k/2k voltage divider to convert the output. But is such a impedance combination low enough to make the Teensy 3.0 ADC happy if its sampling on a differential basis @ 16 bits and a 6MHz internal clock?

I would like to hop back and forth between DAD0 and DAD3 to measure voltage and current. The voltage input circuit uses a AC-coupled adc driver to buffer the signal. I was hoping to avoid using same on the current side if I could.

2. The ADC reference manual (K20P64M50SF0.pdf on Freescale's web site) states that the source time constant should be < 1 ns. That may be excessively conservative, but if it is more than ~ 50 ns, you need to ensure that the C is > 0.1 uF to maintain a 13-bit accuracy. The internal sampling capacitance is about 4 pF, and series resistance is 5k -- so using 1k/2k doesn't significantly affect this.

3. ## K20's A2D impedance vs. Analog signal impedance

Regarding The K20's A2D impedance and consequences for signal impedance:

In Sect. 6.6.1 of http://cache.freescale.com/files/32b...0P64M50SF0.pdf Table 24 gives us:
R_ADIN (multiplexer resistance) of 2K typical, 5K max.

Note 3 in table 23 says that they used a signal with an output impedance of only 8 ohms for measuring the the A2D parameters. Since they almost certainly wanted to show the best specs they can, I'm left wondering about the big difference between 8 ohms and 5K. If somebody wiser than me understands this disparity, please respond here. -- Thanks!

It looks to me that the impedance of C_AS completely dominates the resistive component at the A2D's conversion frequency. With 2 MHz as the worst-case conversion freq. for 16-bit mode, and a 0.1 uFd cap for C_AS, I get Z_CAS = 1/j*2*pi*2e6*1e-7 = 1.25 ohms.

I also note that 16-bit accuracy is apparently only
guaranteed on the differential pins ADCx_DP0, ADCx_DM0, according to the first sentence in Sect. 6.6.1

4. Hi Larry and thanks for your observations!

If my calculations are correct, the allowable source impedance limits for my application range from about 1200 Ohm in default mode (i.e ADLSMP= 0, ADHSC =0) up to 25k Ohm (ADLSMP =1, ADLSTS =00, ADHSC =1)

This is assuming a 48MHz Clock on the MCU, a 8:1 ADC diviser, resulting in a 6MHz ADC Clock. Per the data sheet, the base sample time (assuming one-shot operation) is 6 ADC cycles, i.e 1/1,000,000 of a second. Using this TI literature as guidance (see p. 5) and a input capacitance of 10pF, as well as a input resistance of 6kOhm, as well as m=4 to allow for 1/16th LSB operation, illustrates why the folk at Freescale chose a low source impedance.

Thus, it might be advantageous to slow down the ADC clock further for very high impedance loads. Slower ADC sampling time will then result in a lower overall sampling rate. Lastly, the data sheet recommends use of a 0.01uF capacitor from each analog-in pin to AGND.

5. ## A2D input impedance: c=.01uF difficult to achieve with a timeConst < 1 nanoSecond

Greetings all,

I've noticed something else puzzling re the K20's A2D and suggested circuit elements for best A2D results. I'm seeking any opinions/insights about this apparent strangeness:

In Sect. 6.6.1 of http://cache.freescale.com/files/32b...0P64M50SF0.pdf I see two separate assertions about circuitry to drive A2D channels. The first is that they recommend putting a .01 uF cap (1e-8 Farads) on each A2D pin used. That seems reasonable, to hold a fairly constant voltage, despite the A2D sucking some current -- irregularly -- as the SAR part of the A2D does its thing.

They also recommend that the time constant of any External RC network connected to an A2D pin be < 1 nanoSecond. What is the resistance required to have a 1 nanoSecond (1e-9) time constant? If we ignore inductance (which is dicey at 1 nanoSecond!), then R*C = tau. So R*1e-8 = 1e-9, which gives an answer of R = 0.1 ohms Do I have an error in my math? A time constant of < 1 nanoSec isn't so easy to achieve (especially if one considers inductance as well.) I note that the Kinetis folks used some sort of test gear with an output impedance of 8 Ohms.

Is the correct interpretation instead that the effective series resistance of the 0.01 uF Cap itself must be under 0.1 ohms? Such a cap exists, but it's not your typical ceramic cap. I'm finding only one cap that meets the under a tenth of an ohm ESR after searching via octopart.com. FYI, it's the Cornell Dubilier 940C30S1K(-F) -- and it's both through-hole only and over 1\$(US)/each. Can anybody recommend another 0.01 uF cap with a ESR <= 0.1 ohms? -- Or some other way of meeting the requirements for optimum A2D performance?

6. I sincerely doubt that these requirements are right for our application. They may be what's necessary for sampling at the highest speeds offered by the ADC. To put things in perspective, a nanosecond is 10e-9 seconds. On the other hand, the recommended ADC clock rate for 16 bit operation per the downloadable ADC simulation tools from Freescale is less than 8MHz. At 8MHz and the fastest sampling time possible (consecutive sampling, etc.) you're talking 4 clock cycles minimum for sampling (never mind follow-on processing). That turns into 5e-7s. That in turn would result in 500 time constants passing on the fastest possible sampling rate for 16bit operation. For one-shot operation, you'd have at least 750 time constants per sample. And at a more realistic 6MHz rate for the ADC (it's not easy running it at other speeds than 6 or 3MHz), you'd have 1000 time constants pass on every sample under one-shot conditions.

Simply put, that seems nuts to me.

The TI literature suggests a minimum of about 14 time constants, with additional 16 being beneficial to achieve 1/16th LSB operation. 30 time constants in one-shot, 16 bit operation @ 6MHz and a ADC input resistance of 6kOhm suggests a maximum source resistance of 1213 Ohm. I'm going to be on the bleeding edge using a 1200 Ohm, 0.1% resistor in my voltage divider.

FWIW, I just reviewed the AVX manual and that suggests that standard 1210 C0G/NP0 capacitors will feature a resistance of well below 0.1Ohm (see chart on p. 9). All C0G 0.01uF capacitors with a 0.1% dissipation factor hence appear to be suitable. Through-hole versions can be had at Digikey for as little as 48 cents, while SMT versions are as little as 32 cents (0805). Note: the data sheets on the least expensive units do not list dissipation factors - thus you would need to confirm that elsewhere. However, if you're willing to pay 2x of the minimum, you'll find ceramic capacitors at Digikey that promise a low resistance right in their specification sheets.

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