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Thread: Teensy3, I2C, Multiple Masters

  1. #1
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    Teensy3, I2C, Multiple Masters

    I am experimenting using two T3's, each as a master on an I2C bus. I do not require the Wire.h or i2c_t3.h libs to do any conflict management because I am using a digital input on each T3 to signal to the other that it has the bus. My test was to have them both take turns writing to a LCD display. I am using a test harness that I have used successfully many times before. 3.3V T3 <-> bidirectional level shift <-> 5V LCD

    As often happens, even with things that seem so simple, it didn't go well the first time. My first set of code wasn't quite right and now I have no I2C ability with the two T3's that were connected to the bus. Somehow the I2C ports were both damaged and no longer work. I believe they were both trying to communicate on the bus at the same time. All the details are not know. I connected a known good T3 to the bus, after removing the damaged ones, and it can communicate with the LCD just fine.

    I have a hard time believing that just because there are two masters out of sync on the same buss that the I2C ports would be damaged. I am not familiar with the internal construction of the I2C ports, can someone tell me if it is even possible to damage the ports in the described manner?

    Thanks for your time.

  2. #2
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    There are several ways to damage a pin I/O circuit: OV (over-voltage), OC (over-current), ESD (electro-static discharge), and latchup are some of the big ones.

    I2C pins are open-drain, and the bus requires resistive pullups to establish a logic high. Normally this configuration has inherent current limiting due to the resistive pullups (eg. even if the pin pulls strongly to ground the current limits to whatever the resistor allows - however there is an assumption which I'll get into below).

    Latchup can probably be ignored on the assumption that the original designers knew how to isolate their P-type and N-type devices from each other and establish good substrate connections.

    OV is more of a sustained overvoltage (IIRC there was some other post recently about someone accidentally connecting 18V or some such directly to the pins). Sustained 5V on a T3.0 would probably be a problem.

    ESD is a very high voltage, short duration pulse. All I/Os have some level of ESD protection (GGNMOS, supply/ground diodes, series-R, etc). Could be that your parts got ESD zapped, but the odds of two at once, just seems low...

    OC is another possibility. Now as mentioned above normally current is limited, but the assumption is that the only logic-high source on the bus is your resistive pullup. If one of the devices got configured as a digital output at the same time the other was open-drain outputting a logic low, then the 1st device would directly source it's supply into the 2nd devices short-to-ground. I'm not sure what the current would be, or how long it could sustain.

    Similar OC condition could be say mis-wiring a breadboard to connect 5V directly to the bus lines. That would be essentially a resistive pullup of zero ohms, so if each device in turn tried to output a logic low it could have burned out the pulldown device (or the internal wiring to the device). For example, a 5V connection to a pulldown NMOS with an Ron of 10ohms, would try to push half an Amp through the pin, it would definitely pop (barring some series-R limiter in the ESD structure, which I doubt for this configuration).

    Just guesses here, it is impossible to predict what happened other than to say there are a few possibilities.

  3. #3
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    A simple test is to treat the i2c clock and data pins as general purpose outputs and then send a series of pulses out the outputs and see if they are toggling on a scope.

    I have inadvertently grounded an output pin. Sometimes it blows the pin, sometimes it doesn't.

  4. #4
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    Well, I found the problem and kinda hate to say what it was. The bread board I was using was faulty.

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