surixurient
Member
Hi, is there a list of the pin configurations? PORT_PCR_MUX
for each pin.
Thanks
for each pin. Thanks
list of pin modes for teensy 3.1?
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PencilGeek
Member
Hi, is there a list of the pin configurations? PORT_PCR_MUX
Thanks
/*---------------------------------------------------------------------
* Set Pin Control Register as follows (Register: PORTx_PCRn):
* MUX : Pin Mux Control, sets pin definition according to table
* in K20 Manual, Section 10.3.1,
* "K20 Signal Multiplexing and Pin Assignments"
* ------------------------------------------------------------------*/
https://www.pjrc.com/teensy/K20P64M72SF1RM.pdf
surixurient
Member
Thanks. Is there a mapping from the k20 pin numbers to the teensy's? I took the port numbers from pins_teensy to map but it doesnt seem to match up.
on the teensy it says 3,4,5,6 9,10 and 20,21,22,23 have PWM functionality. but when i look at those pins in the k20 chart Iits not clear to me how to do PWM
here is the mapping I tried to make.
on the teensy it says 3,4,5,6 9,10 and 20,21,22,23 have PWM functionality. but when i look at those pins in the k20 chart Iits not clear to me how to do PWM
here is the mapping I tried to make.
Code:
pin port bit k20 pin alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 alt8
0 b 16 39
1 b 17 40
2 d 0 57
3 a 12 28 CMP2_IN0 PT-A12 CAN0_TX FTM1_CH0 I2S0_TXD0 FTM1_QD_PHA
4 a 13 29 CMP2_IN1 PT-A13/LLWU_P4 CAN0_RX FTM1_CH1 I2S0_TX_FS FTM1_QD_PHB
5 d 7 64 PT-D7 CMT_IRO UART0_TX FTM0_CH7 FTM0_FLT1
6 d 4 61 PT-D4/LLWU_P14 SPI0_PCS1 UART0_RTS_b FTM0_CH4 FB_AD2 EWM_IN
7 d 2 59
8 d 3 60
9 c 3 46 CMP1_IN1 PT-C3/LLWU_P7 SPI0_PCS1 UART1_RX FTM0_CH2 CLKOUT I2S0_TX_BCLK
10 c 4 49 PT-C4/LLWU_P8 SPI0_PCS0 UART1_TX FTM0_CH3 FB_AD11 CMP1_OUT
11 c 6 51
12 c 7 52
13 c 5 50
14 d 1 58
15 c 0 43
16 b 0 35
17 b 1 36
18 b 3 38
19 b 2 37
20 d 5 62 ADC0_SE6b PT-D5 SPI0_PCS2 UART0_CTS_b FTM0_CH5 FB_AD1 EWM_OUT_b
21 d 6 63 ADC0_SE7b PTD6/LLWU_P15 SPI0_PCS3 UART0_RX FTM0_CH6 FB_AD0 FTM0_FLT0
22 c 1 44 ADC0_SE15/TSI0_CH14 PTC1/LLWU_P6SPI0_PCS3 UART1_RTS_b FTM0_CH0 FB_AD13 I2S0_TXD0
23 c 2 45
24 a 5 27
25 b 19 42
26 e 1 2
27 c 9 54
28 c 8 53
29 c 10 55
30 c 11 56
31 e 0 1
32 b 18 41
33 a 4 26
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PencilGeek
Member
I used the pinout from the teensy schematic and looked them up in the table. I looked them up by name, not pin number. I mapped the pin name to the table in 10.3.1. I was only interested in the FTM channels, and I didn't notice any errors in the ones I checked.
I believe (may be wrong) that you can do PWM on anything controlled by an FTMx-CHn. So that would be pins 5, 6, 9, 10, 20, 21, 22, 23 for FTM0. Pins 3, 4 for FTM1. Pins 32, 25 for FTM2. You missed 25, 32 for ALT-3 on FTM2 in your list.
Last edited:
surixurient
Member
Thanks, that makes sense now.
surixurient
Member
here is some better formatting steve
| pin | port | bit | k20 pin | alt0 | alt1 | alt2 | alt3 | alt4 | alt5 | alt6 | alt7 | alt8 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | b | 16 | 39 | |||||||||
| 1 | b | 17 | 40 | |||||||||
| 2 | d | 0 | 57 | |||||||||
| 3 | a | 12 | 28 | CMP2_IN0 | PTA12 | CAN0_TX | FTM1_CH0 | I2S0_TXD0 | FTM1_QD_PHA | |||
| 4 | a | 13 | 29 | CMP2_IN1 | PTA13/LLWU_P4 | CAN0_RX | FTM1_CH1 | I2S0_TX_FS | FTM1_QD_PHB | |||
| 5 | d | 7 | 64 | PTD7 | CMT_IRO | UART0_TX | FTM0_CH7 | FTM0_FLT1 | ||||
| 6 | d | 4 | 61 | PTD4/LLWU_P14 | SPI0_PCS1 | UART0_RTS_b | FTM0_CH4 | FB_AD2 | EWM_IN | |||
| 7 | d | 2 | 59 | |||||||||
| 8 | d | 3 | 60 | |||||||||
| 9 | c | 3 | 46 | CMP1_IN1 | PTC3/LLWU_P7 | SPI0_PCS1 | UART1_RX | FTM0_CH2 | CLKOUT | I2S0_TX_BCLK | ||
| 10 | c | 4 | 49 | PTC4/LLWU_P8 | SPI0_PCS0 | UART1_TX | FTM0_CH3 | FB_AD11 | CMP1_OUT | |||
| 11 | c | 6 | 51 | |||||||||
| 12 | c | 7 | 52 | |||||||||
| 13 | c | 5 | 50 | |||||||||
| 14 | d | 1 | 58 | |||||||||
| 15 | c | 0 | 43 | |||||||||
| 16 | b | 0 | 35 | |||||||||
| 17 | b | 1 | 36 | |||||||||
| 18 | b | 3 | 38 | |||||||||
| 19 | b | 2 | 37 | |||||||||
| 20 | d | 5 | 62 | ADC0_SE6b | PTD5 | SPI0_PCS2 | UART0_CTS_b | FTM0_CH5 | FB_AD1 | EWM_OUT_b | ||
| 21 | d | 6 | 63 | ADC0_SE7b | PTD6/LLWU_P15 | SPI0_PCS3 | UART0_RX | FTM0_CH6 | FB_AD0 | FTM0_FLT0 | ||
| 22 | c | 1 | 44 | ADC0_SE15/TSI0 | PTC1/LLWU_P6 | SPI0_PCS3 | UART1_RTS_b | FTM0_CH0 | FB_AD13 | I2S0_TXD0 | ||
| 23 | c | 2 | 45 | ADC0_SE4b/CMP1/TSI0 | PTC2 | SPI0_PCS2 | UART1_CTS_b | FTM0_CH1 | FB_AD12 | I2S0_TX_FS | ||
| 24 | a | 5 | 27 | |||||||||
| 25 | b | 19 | 42 | TSI0_CH12 | PTB19 | CAN0_RX | FTM2_CH1 | I2S0_TX_FS | FB_OE_b | FTM2_QD_PHB | ||
| 26 | e | 1 | 2 | |||||||||
| 27 | c | 9 | 54 | |||||||||
| 28 | c | 8 | 53 | |||||||||
| 29 | c | 10 | 55 | |||||||||
| 30 | c | 11 | 56 | |||||||||
| 31 | e | 0 | 1 | |||||||||
| 32 | b | 18 | 41 | TSI0_CH11 | PTB18 | CAN0_TX | FTM2_CH0 | I2S0_TX_BCLK | FB_AD15 | FTM2_QD_PHA | ||
| 33 | a | 4 | 26 |
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