How can I work this way with the Teensy 3.1? Anyone can say what are the T3.1 I/O ports?
They're documented in chapter 49, starting on page 1331.
http://www.pjrc.com/teensy/K20P64M72SF1RM.pdf
Which pins are which native port and bit are documented in the schematic
http://www.pjrc.com/teensy/schematic.html
and also in core_pins.h
https://github.com/PaulStoffregen/cores/blob/master/teensy3/core_pins.h#L50
Each native port has 3 registers, for output, input and direction, very similar to the AVR registers. There's also 3 more write-only registers, for setting, clearing and toggling output bits (without having to read).
Unlike AVR, there's also a pin config register for every single pin. Those are documented in chapter 11. On AVR, the pins default to input mode. On Kinetis, they default to disabled. The pin has to be explicitly configured to be GPIO (or any of the peripherals). On AVR, most pins automatically are taken over when you turn on the peripherals. Some are half-consumed, but the DDR register still works. On Kinetis, the pins have an 8-way mux that controls which thing is controlling the pin.
The config registers also control the pullups, pin interrupts and other features. It's all documented in chapter 11 and 49.
Those GPIO registers (chapter 49) are 32 bits. You can write to all 32 bits at once, or just 16 bits (either half), or just 8 bit (any of the 4 bytes). The 8 and 16 bit writes chance only that portion and leave the rest of those 32 bit untouched.
