Help needed with DIY teensy please!

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mattomatto said:
Although i clearly have more to learn, i do know everything you just mentioned, but couldnt make it fit any better on a 2 layer board. I honestly have no idea how to route that board with fewer vias. I didnt include decoupling caps on the mini54 people paul's schematic didnt have them. I've used that crystal because its cheap and performs the same.
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Decoupling caps belong on every power supply into a chip. They keep digital noise in (if applicable) and keep the chip well-hydrated re: power. Whether or not Paul showed the decoupling cap at the Mini 54, follow good practices, and don't just blindly copy. That reminds me of an old trade-show related tale where allegedly a British manufacturer displayed a pump with a non-sensical bolt placed into the volute and then delighted in discovering / publicizing how their far-east competition slavishly copied the design- down to the non-sensical bolt.

mattomatto said:
When you say the 'ground plane isn't used on one side' do you mean that I have not filled the top layer with another ground plane? Surely that just means you have to cut through the ground plane constantly which is bad?
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FWIW, for 2-layer designs I avoid using one side for anything but GND. The other side gets signals, power traces, and so on. Any unused space on the signal/power side gets tied via multiple vias to the gnd plane on the other side. For example, the Mini54 daughterboard has zero signal or power-related vias. All Vias are strictly there to tie the top and bottom GND to each other.

If you understood all these principles, then I struggle to understand why you'd via the PGM button connection to the Mini54, for example. There was no reason to use a via, you had a clear shot at connecting the PGM signal directly to the chip. Your decoupling caps weren't tied directly to the GND plane either, nor the VSS pins on the chip. That chip should be sitting in a vast sea of GND seeing that so few pins are actually connected to anything.

When you redesign your boards, I suggest you see how you can accommodate the needs of both boards in terms of your header and pin selection. The current design is dense, easy to solder and hard to route to well. Alternative approaches to the header selection and pin designation may make for a easier routing exercise.

Apologies, but I'll re-iterate my suggestion to abandon the bare metal approach for now and focus on getting a working product (even if it sells at a higher price in lower volumes) and only then investing the engineering to make a lower-cost bare metal system if demand and interest warrant it.
 
OK thanks, constantine. Just one more question for now... Surely it's actually impossible to route all signal and power traces on one side? Everything I've read on 2 layer design says not to worry too much about using vias through the ground plane because it's inevitable.

I honestly didn't think sending the pgm signal through the ground plane would make an ounce of difference! I suppose its all cumulative right....
 
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I avoid vias for anything but GND where I can. The mini 54 daughter-board has zero signal/power vias, for example. That, despite also featuring the usb connection, a header for a GPS module, a battery backup for the GPS, some tvs diodes, a poly fuse, etc.

My power meter motherboard has two power vias and one very short via for the SCL. The cumulative length of all three together is less than 1/2". The GPRS module has two power vias. The 1-wire board has three vias, iirc.

Etc.

If you work the problem long and hard enough, you can minimize vias for signals and power while also maintaining good decoupling / gridded power and GND connections and so on. See the stuff that Ott has published as well as some of the articles at analog devices, national semi, TI, maxim, among others.

Current has to return and for high speed signals it will return on the GND plane underneath the signal trace, not the path of lowest resistance. So I design my boards with lots of decoupling caps, lots of GND vias, and a big emphasis on ensuring a continuous ground plane wherever possible to minimize the possibility of EMI... and despite all that, I still have issues with getting my 2-layer designs to be as out-of-the-box usable as Paul's standard level of excellence when it comes to the Teensy.

Going down the path to developing your own boards is fraught with risk, which is why I keep reiterating that for most folk it makes more sense to simply go the route of incorporating headers into their design for a standard teensy 3, figure out if there is a market (before you accumulate a boxful of bad PCBs), and only then considering going bare-metal (IF that makes sense) with JTAG-compatible rig. The only reason I deviated from this approach in my project is space - I couldn't fit a Teensy into a specific enclosure and accommodate all the other stuff I wanted in there. But I've paid the price in terms of a slow development effort, multiple iterations, etc. and I am nowhere near a final prototype.
 
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Follow-up:

One of my boards that was not uploading consistently featured a reset signal on the wrong pin for the MK20. So, it's a miracle that the chip allowed uploads at all.

Similarly, that board features a dead RTC section in the MK20 - I have DMM'd the RTC pins with 9+Megs of resistance, and exchanging one of the RTC crystals for another one. My guess is that I must have fried it somehow.
 
Good to know you found the issue. I left pins 19,20 &21 unconnected on my schematic since I'm not using the RTC - that shouldn't cause problems should it?

Cracking on with a second attempt now!
 
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