How does SPI Transactions stand now, for use with real-time SPI devices that interrupt upon an event, such as message arrivals in communications (wireless, ethernet, etc), or any other such device?
With just one such real-time device... when there are is no other transaction in progress, the real-time SPI device's interrupt can be safely enabled. When there is a brief transaction, the interrupt is masked until that transaction completes its use of the shared SPI port. If a real-time event occurred while the other transaction was using the SPI port, the real-time device's ISR would be delayed - which is OK if the delay due to interrupt masking is not so long as to block another real time event.
With 2+ such real-time devices, each with an ISR using the SPI, one can do as the above, disabling both ISRs while a transaction is using the SPI. This assumes that the two real-time SPI devices do not allow nested interrupts, i.e., where one can interrupt the other's ISR - as doing so would cause the SPI port ownership exclusion scheme to fail.
Besides communications devices that interrupt based on messages (received and transmit complete), there are multi-channel SPI ADCs that might interrupt every 100uSec and the ISR wants to quickly read and store a sample. With the high interrupt rate, these are a challenge.
So what's the status ?
With just one such real-time device... when there are is no other transaction in progress, the real-time SPI device's interrupt can be safely enabled. When there is a brief transaction, the interrupt is masked until that transaction completes its use of the shared SPI port. If a real-time event occurred while the other transaction was using the SPI port, the real-time device's ISR would be delayed - which is OK if the delay due to interrupt masking is not so long as to block another real time event.
With 2+ such real-time devices, each with an ISR using the SPI, one can do as the above, disabling both ISRs while a transaction is using the SPI. This assumes that the two real-time SPI devices do not allow nested interrupts, i.e., where one can interrupt the other's ISR - as doing so would cause the SPI port ownership exclusion scheme to fail.
Besides communications devices that interrupt based on messages (received and transmit complete), there are multi-channel SPI ADCs that might interrupt every 100uSec and the ISR wants to quickly read and store a sample. With the high interrupt rate, these are a challenge.
So what's the status ?