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Thread: audio lib / slave mode / codec (suggestions ?)

  1. #1
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    audio lib / slave mode / codec (suggestions ?)

    now that the audio library happened, and with teensy 3++ on the horizon, i thought i resurrect an older project of mine (from the days of hyple i2s), which used a wm8731 (in master mode) --

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    now, i figured i'd like to try this in slave mode and, while i'm at it, why not try something slightly more fancy. i'd like to stick with some TSSOP device, so i'm looking at CS4272 and WM8778.

    any alternative suggestions? anyone using slave mode (anything i need to know?)

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    Senior Member PaulStoffregen's Avatar
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    I2S slave mode is basically untested. If you're willing to endure some problems and help test and fix issues, doing so would be a really noble effort that might really help others who come after you.

    If you want stuff to just work, I'd highly recommend taking the well worn path of running Teensy 3.1 in I2S master mode.

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    ok, i see. i was under the impression people had been using the 'slave' object with the mikroe board etc.

    i want the stuff to mostly just work, so i'll see to have it support either mode.

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    Senior Member onehorse's Avatar
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    OK, I am struggling with coming up to speed on all things audio.

    I want to add stereo digital I2S-outputting microphones to a Teensy 3.1. The ones I have in mind take a CLK and WS (word or frame select) signal from a master (the Teensy 3.1) and output serial I2S data (left and right) . The output is 24 bits per channel with 2 x 32 clock cycles per stereo data-word and with CLK signals @ 0.5 -3.2 MHz.

    This sounds like I2S master mode to me.

    So some questions:

    Can I just hook up the three wires directly to a Teensy 3.1 (pins 11, 13, 23) and 'read' the I2S data streaming from the microphones?

    Can I also use the audio library to FFT or do other processing on the I2S 'data'?

    Do I need the audio board to capture the I2S 'data'?

    I admit to noob status here, and I am trying to get my arms around just thinking about this problem, so any help with getting my thinking straight would be well appreciated!

    Oh, and can I use an alternate pin rather than pin 23, closer to 11 and 13 for LRCLK (word select)?
    Last edited by onehorse; 11-24-2014 at 10:30 PM.

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    Quote Originally Posted by onehorse View Post
    This sounds like I2S master mode to me.

    So some questions:

    Can I just hook up the three wires directly to a Teensy 3.1 (pins 11, 13, 23) and 'read' the I2S data streaming from the microphones?
    true, though that's a different question.

    i'm not familiar with this device but looks as if your chances aren't bad; it might need some adjustments, i don't know.

    i think the connection at any rate would be:

    BCLK (9) - > SCK
    I2S_RX (13) - > SD
    LRCLK (23) - > WS
    GND or VDD - > L/R

    Do I need the audio board to capture the I2S 'data'?
    no, unless you wanted to use the sgtl5000 codec. probably a good idea though to go with something that works first.

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    Senior Member onehorse's Avatar
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    Thanks for the reply!

    I don't want to use a codec; my end is not audio per se but the doppler shift between to separated microphones. So I want to capture the I2S serial data from each separate 'phone and do math operations on the respective collection. I chose a microphone with an embedded DSP that provides an I2S interface to avoid having to use a codec. I want to spew the audio data directly into the microcontroller for processing; I am space constrained and want to minimize the number of components I need to use.

    Do I need an MCLK signal? Is the BCLK the Teensy 3.1 master clock output that the slave mics require? What is the difference between MCLK and BCLK? I have noticed in some code examples BCLK is set to be equal to MCLK.

    I would really like to have the LRCLK pin near pins 9, 11, 13 to make for a small add-on shield for the Teensy. If there is no pin 23 alternative, I guess I will just have to be satisfied with the breadboard solution or a long green wire.

    I am assuming the L/R refers to the left or right microphone select digital signals. That part, at least, I understand how to do!

    Thanks for the help.

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    Quote Originally Posted by onehorse View Post
    Do I need an MCLK signal? Is the BCLK the Teensy 3.1 master clock output that the slave mics require? What is the difference between MCLK and BCLK? I have noticed in some code examples BCLK is set to be equal to MCLK.
    no, in this case you don't need it, i think.

    the main problem i can see is that the audio library is 16 bit, whereas your device seems to be 24 bit.

    Quote Originally Posted by onehorse View Post
    I would really like to have the LRCLK pin near pins 9, 11, 13 to make for a small add-on shield for the Teensy.
    yes, there's alternate pins. i believe LRCLK/I2S0_TX_FS is also on pin 4.

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    Quote Originally Posted by PaulStoffregen View Post
    I2S slave mode is basically untested. If you're willing to endure some problems and help test and fix issues, doing so would be a really noble effort that might really help others who come after you.

    If you want stuff to just work, I'd highly recommend taking the well worn path of running Teensy 3.1 in I2S master mode.
    Just popped by to see what is happening lately. I would swear I posted a fully working example of switching the SGTL5000 to behave as master on the I2S bus in the 'Audio Library' thread a fair while back, by memory my example drove it to either 48KS/s or 96KS/s and when I tested it it worked easily with all the objects in the library that do not arbitrarily rely on the 44.1KS/s. It was not much of a feat, I've been very busy with other stuff my work wants but I am going to get to return to 'playing' with the SGTL5000 for them before too much longer.

    If there was much clamour for help in enabling other sample rates in the audio adapter I would at least dig up the example I posted to Audio Library thread and explain it a bit. I'd probably explain it a lot if pressed.

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    Quote Originally Posted by robsoles View Post
    I would swear I posted a fully working example of switching the SGTL5000 to behave as master on the I2S bus in the 'Audio Library' thread a fair while back, by memory my example drove it to either 48KS/s or 96KS/s and when I tested it it worked easily with all the objects in the library that do not arbitrarily rely on the 44.1KS/s. It was not much of a feat, I've been very busy with other stuff my work wants but I am going to get to return to 'playing' with the SGTL5000 for them before too much longer.
    ah right, found it. it's post #573 in that huge thread.

    Quote Originally Posted by robsoles View Post
    If there was much clamour for help in enabling other sample rates in the audio adapter I would at least dig up the example I posted to Audio Library thread and explain it a bit. I'd probably explain it a lot if pressed.
    not yet ... though that might happen.

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    Senior Member PaulStoffregen's Avatar
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    Quote Originally Posted by onehorse View Post
    Do I need an MCLK signal?
    It seems the INMP441 does not need MCLK.

    But it does requires BCLK to be 64X the data rate. The I2S master object currently creates BCLK at 32X the data rate, so some tough hacking in the I2S code will probably be needed.

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    That sounds as if the I2S Master object should have a method to set BCLK multiplier, which defaults to 32X ?

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    slightly (well, only mildly) OT, but then this whole thread is.

    quoting Paul from another forum/thread:

    Anyway, the underlying software support is there for streaming to the SD card, so in theory a stand alone sampler could be built.
    as above mentioned board will have a codec + the SD (+ the flash IC), any intuitions on how (well) this (ie sampling) will/might work? ie will SD record and SD play play nicely together? - ie for overdubbing etc. or i'm guessing it might need some more elaborate interleaving of write/read?

    i figure though it must be entirely possible. the EHX 2880 looper seems to have managed two stereo tracks with just (?) SD card very well (something else might have been involved, i had never looked inside)

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    I2S BCLK multiplier

    Quote Originally Posted by PaulStoffregen View Post
    It seems the INMP441 does not need MCLK.

    But it does requires BCLK to be 64X the data rate. The I2S master object currently creates BCLK at 32X the data rate, so some tough hacking in the I2S code will probably be needed.

    How tough? The BC127 bluetooth module also requires at least a 64x BCLK to work in slave mode. Seems like PTC3 is involved, but I haven't yet found where that is configured and would appreciate knowing if I am barking up the right tree.
    Last edited by Alex Stahl; 07-19-2016 at 11:05 PM.

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    IS2 BCLK multiplier

    Quote Originally Posted by Alex Stahl View Post
    How tough? The BC127 bluetooth module also requires at least a 64x BCLK to work in slave mode. Seems like PTC3 is involved, but I haven't yet found where that is configured and would appreciate knowing if I am barking up the right tree.
    Digging a little deeper, looks like I need to change bits 7-0 of I2s0_TCR2. I'm using a Teensy 3.2 and understand that a generalised solution would be more involved, however I am on a deadline to do a proof of concept. Any pointers would be most appreciated. Thanks!

  15. #15
    Senior Member PaulStoffregen's Avatar
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    Do you have a scope or logic analyzer capable of capturing BCLK and LRCLK? Or maybe 2 frequency counters? (typically hand-held multimeters can't measure up into the MHz range on their frequency modes)

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    Hi Paul,

    Thanks for your reply. I know you're busy with the new board, and that's pretty exciting!

    Yes I have a dual-channel 100Mhz scope (Tektronix, I'm from Beaverton after all) and have been experimenting with various registers, primarily in output_i2s.cpp.

    If I change the bit clock divider (I2S_TCR2_DIV and I2S_RCR2_DIV) from 3 to 1 I get a BCLK at 2.82Mhz, i.e. 64x Fs. So that's promising. But the LRCLK also doubles to 88.2kHz, hmm. Tried increasing I2S_TCR4_SYWD to 31, but it can't be bigger than the word size.

    Next I changed CORE_PIN11_CONFIG to output the RX BCLK, and now have a 44.1kHz LRCLK on pin 23 and a 2.82Mhz BCLK on pin11. Don't think I need MCLK in our product so maybe this hack will get me going.

    One thing I noticed that may be more generally salient, is that the default output_i2s.cpp sets both TX and RX as synchronous (I2S_xxR2_SYNC = 1). The K20 manual sez that if either one of the SAI TX or RX is synchronous, the other must be asynchronous. When I changed that, the 88.2kHz BCLK become a lot less jittery, fwtw.

    Code:
    	// configure transmitter
    	I2S0_TMR = 0;
    	I2S0_TCR1 = I2S_TCR1_TFW(1);  // watermark at half fifo size
    	I2S0_TCR2 = I2S_TCR2_SYNC(1) | I2S_TCR2_BCP | I2S_TCR2_MSEL(1)
    //		| I2S_TCR2_BCD | I2S_TCR2_DIV(3);
                    | I2S_TCR2_BCD | I2S_TCR2_DIV(1);
    	I2S0_TCR3 = I2S_TCR3_TCE;
            I2S0_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(15) | I2S_TCR4_MF
    		| I2S_TCR4_FSE | I2S_TCR4_FSP | I2S_TCR4_FSD;
            I2S0_TCR5 = I2S_TCR5_WNW(15) | I2S_TCR5_W0W(15) | I2S_TCR5_FBT(15);
    
    	// configure receiver (sync'd to transmitter clocks)
    	I2S0_RMR = 0;
    	I2S0_RCR1 = I2S_RCR1_RFW(1);
    //     I2S0_RCR2 = I2S_RCR2_SYNC(1) | I2S_TCR2_BCP | I2S_RCR2_MSEL(1)
            I2S0_RCR2 = I2S_RCR2_SYNC(0) | I2S_TCR2_BCP | I2S_RCR2_MSEL(1)    //see p.1314 of K20 manual--
    //		| I2S_RCR2_BCD | I2S_RCR2_DIV(3);
                    | I2S_RCR2_BCD | I2S_RCR2_DIV(3);
    	I2S0_RCR3 = I2S_RCR3_RCE;
    //	I2S0_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(31) | I2S_RCR4_MF   //nice try, SYWD must be less than WNW
            I2S0_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(15) | I2S_RCR4_MF
    		| I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD;
    	I2S0_RCR5 = I2S_RCR5_WNW(15) | I2S_RCR5_W0W(15) | I2S_RCR5_FBT(15);
    
    	// configure pin mux for 3 clock signals
    	CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK)
    	CORE_PIN9_CONFIG  = PORT_PCR_MUX(6); // pin  9, PTC3, I2S0_TX_BCLK
    //	CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK
            CORE_PIN11_CONFIG = PORT_PCR_MUX(4); // pin 11, PTC6, I2S0_RX_BCLK
    It prolly shows, I have much more experience debugging hardware and interface firmware than DMA coding. I've had glimmers of increasing the wordlength, frame size, and/or sample rate and then masking off the extra bits so Teensy still sees stereo 16/44.1, but I haven't grokked how BCLK truly relates to FIFO DMA, etc. etc.

    Happy to try any suggs, this is one of several new I2S projects so it's all good learning curve.

    Thanks!
    -alex

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    Glancing back at the start of this thread that I totally co-opted, I want to mention that helping test and debug Teensy in I2S slave mode is also something I am more than happy to do. For a future project I'll want an external precision audio clock as master.

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