Hi,
So I've run into a little problem and I'm trying to make sure everything is ok before I proceed.
I plan to have 3 devices on the T3.1 Hardware SPI bus.
1x ILI9341 2.2" LCD
1x SDCard
1x Freescale 33977
The ILI9341 and SD card are both 3v3 Logic devices, however the 33977 is a 5V logic device.
By itself the logic high input the 33977 is >2.0v and the serial in pins on the T3.1 are 5V compliant, so the device works ok.
My concern is connecting it to a shared bus where the MISO, MOSI, SCLK are all shared among devices, could the 5V signal on MISO from the 33977 harm the other devices on the bus when it is transmitting?
or when CS is not asserted on these devices (display/SDCard) does their respective MISO lines go High-Z or similar?
If this couldn't be guaranteed (how could I check?) could I use a simple level shifter on the MISO from the 33977 to ensure a proper design of the bus?
Or could I use a SoftSPI (shiftOut(),ShiftIn()) implementation (on separate pins) but would have to modify these with delays to not exceed a 2.0MHz SPI Speed for the 33977 which would otherwise be managed by SPI transactions (also the 33977 uses 16 bit transfers which would be preferred for Hardware SPI on the T3.1)
Advice/Suggestions/Insight?
Thanks
So I've run into a little problem and I'm trying to make sure everything is ok before I proceed.
I plan to have 3 devices on the T3.1 Hardware SPI bus.
1x ILI9341 2.2" LCD
1x SDCard
1x Freescale 33977
The ILI9341 and SD card are both 3v3 Logic devices, however the 33977 is a 5V logic device.
By itself the logic high input the 33977 is >2.0v and the serial in pins on the T3.1 are 5V compliant, so the device works ok.
My concern is connecting it to a shared bus where the MISO, MOSI, SCLK are all shared among devices, could the 5V signal on MISO from the 33977 harm the other devices on the bus when it is transmitting?
or when CS is not asserted on these devices (display/SDCard) does their respective MISO lines go High-Z or similar?
If this couldn't be guaranteed (how could I check?) could I use a simple level shifter on the MISO from the 33977 to ensure a proper design of the bus?
Or could I use a SoftSPI (shiftOut(),ShiftIn()) implementation (on separate pins) but would have to modify these with delays to not exceed a 2.0MHz SPI Speed for the 33977 which would otherwise be managed by SPI transactions (also the 33977 uses 16 bit transfers which would be preferred for Hardware SPI on the T3.1)
Advice/Suggestions/Insight?
Thanks