Hi..
maybe i've found a new undocumented feature.. i don't know how to test it, because i don't have the technical equipment.
Example, for Port D:
#define PORTD_DFER (*(volatile uint32_t *)0x4004C0C0) // Digital Filter Enable Register
#define PORTD_DFCR (*(volatile uint32_t *)0x4004C0C4) // Digital Filter Clock Register
#define PORTD_DFWR (*(volatile uint32_t *)0x4004C0C8) // Digital Filter Width Register
See description in http://cache.freescale.com/files/mi...ORMAT=pdf&WT_ASSET=Documentation&fileExt=.pdf (a different chip) These registers were added 2014 to this document and were not describd before.
We have a short note in "5.7.4 PORT digital filter clocking" in "our" refmanual too, but the rest is missing.
The registers are readable and writeable on the teensy3.1
It would be great if someone could test if the filters work !!
maybe i've found a new undocumented feature.. i don't know how to test it, because i don't have the technical equipment.
Example, for Port D:
#define PORTD_DFER (*(volatile uint32_t *)0x4004C0C0) // Digital Filter Enable Register
#define PORTD_DFCR (*(volatile uint32_t *)0x4004C0C4) // Digital Filter Clock Register
#define PORTD_DFWR (*(volatile uint32_t *)0x4004C0C8) // Digital Filter Width Register
See description in http://cache.freescale.com/files/mi...ORMAT=pdf&WT_ASSET=Documentation&fileExt=.pdf (a different chip) These registers were added 2014 to this document and were not describd before.
We have a short note in "5.7.4 PORT digital filter clocking" in "our" refmanual too, but the rest is missing.
The registers are readable and writeable on the teensy3.1
It would be great if someone could test if the filters work !!
Last edited: