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Thread: Coming Soon: Teensy-LC (low cost Teensy)

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  1. #11
    Senior Member
    Join Date
    Jun 2013
    So. Calif
    UART and DMA
    I've been using UART TX DMA - to offset the lack of hardware FIFOs in the UARTs. A 16 deep FIFO (common in UARTS) can interrupt at 75% or so, and thereby reduce the interrupts per second by more than a factor of 10.
    At 115.2Kbaud and without a FIFO and no DMA, that's 11,000 interrupts per second. It's not that a UART sustains that rate, but the burst of interrupts can disrupt other code's timing. And even 11K/sec requires some decent interrupt latency and no sloppy code that blocks interrupts too long.

    Some M4's also lack a hardware timer in the UART to interrupt on the receive side if n character times go by with no (more) incoming data. Data Timeout some say.This helps a bit. The NXP ARM7's had a good UART.
    One case I saw, and want to implement, is to use one of the ARM's timers, where the timer reset cause is setup to be a transition on the UART RX pin. Thus, when RX data ceases, or never occurred, the timer interrupts and one can attend to the UART RX.
    Another case I saw was setting up RX DMA with a circular buffer, and have the DMA interrupt when the DMA address wraps the circular buffer.. that being a counter that was set when the circular buffer's address and size was sent to the DMA controller. I suppose a timer is also needed, for the no-data-present case.

    Why do they cheap-out and use UARTs lacking FIFOs??? How much $ can that save?
    Last edited by stevech; 01-28-2015 at 03:34 AM.

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