#include <SPI.h>
#define CSPIN 6
void setup() {
// comment these out if using the normal SPI pins
SPI.setSCK(14); // Audio shield has SCK on pin 14
SPI.setMOSI(7); // Audio shield has MOSI on pin 7
SPI.begin();
pinMode(CSPIN, OUTPUT);
digitalWrite(CSPIN, HIGH);
while (!Serial) ;
delay(100);
Serial.print("ID bytes: ");
uint8_t id[3];
SPI.beginTransaction(SPISettings(50000000, MSBFIRST, SPI_MODE0));
digitalWrite(CSPIN, LOW);
SPI.transfer(0x9F);
id[0] = SPI.transfer(0);
id[1] = SPI.transfer(0);
id[2] = SPI.transfer(0);
digitalWrite(CSPIN, HIGH);
SPI.endTransaction();
Serial.printf("%02X %02X %02X\n", id[0], id[1], id[2]);
}
void loop() {
}
These SPI flash chips all have discoverable via JEDEC standard commands, to find the chip sizing, sector size list, etc.
8.2.30 Read SFDP Register (5Ah)
The W25Q128BV features a 256-Byte Serial Flash Discoverable Parameter (SFDP) register that contains information about device configurations, available instructions and other features. The SFDP parameters are stored in one or more Parameter Identification (PID) tables. Currently only one PID table is specified, but more may be added in the future. The Read SFDP Register instruction is compatible with the SFDP standard initially established in 2010 for PC and other applications, as well as the JEDEC standard JESD216 that is published in 2011. Most Winbond SpiFlash Memories shipped after June 2011 (date code 1124 and beyond) support the SFDP feature as specified in the applicable datasheet.
I just redesigned the 1 Gbit SPI flash board to use the N25Q00AA Micron chip with one CS. This new board will be made available for sale at Tindie in a few weeks.
The same design can accomodate the 2 Gbit Micron chip also, but I am not sure whether the demand for the extra 1 Gbit justifies the doubling in cost for this new chip. We'll see..
I just redesigned the 1 Gbit SPI flash board to use the N25Q00AA Micron chip
Looks like writing software is easier...4-5. Chip Read and Erase Differences
The Micron N25Q00A only supports the Die Erase func
tion, which means users have to execute four Die
Erase Commands (once in each die) to finish a chip
erase operation. In the meantime, The Macronix
MX66L1G45G device looks and works like a monolithic
1Gb die and only needs one CE command with
no address required.
Similarly, because Micron treats its four die solut
ion as four independently addressable arrays, extra
steps may be required when using the Micron flash d
uring Reads which are not required for the Macronix
flash. For example, per the Micron datasheet "After
any READ command is executed, the device will
output data from the selected address in the die. A
fter a die boundary is reached, the device will sta
rt
reading again from the beginning of the same 256Mb
die. A complete device reading is completed by
executing READ four times.." Macronix has no such
requirement: “the whole memory can be read out
with a single READ instruction. The address counter
rolls over to 0 when the highest address has been reached"
not adding a 9V boost converter to the board?
replace the N25Q00AA with the Macronix MX66L1G45G
It means that it's a bit complicated to use SPI with FIFO when crossing the die-boundaries.
@Paul, what do you think ?
Does anyone know where to buy qty 1 or 2 of the Macronix MX66L1G45G chip? I see Future has them in stock, but a 44 piece minimum for the 3.3V version.
Try this web page
Do you have any of the larger chips handy? Could you run a test program for me, to read their ID bytes?
edit: here's the test:
Is it possible to share your library with other on this forum?