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Thread: Memory board add-on requirements

  1. #176
    Senior Member PaulStoffregen's Avatar
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    Oh, yeah, for other chips with the QSPI ports, you'd want access to those 2 pins.

    Today relatively few microcontrollers have QSPI, but it's probably going to become more common over the next few years.

  2. #177
    Senior Member onehorse's Avatar
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    Interestingly, the ESP8266 supports QSPI. So does the STM32L4 which I am trying to use. Anyway, there is no real downside having the resistors there. It does make it possible for people to not even connect these pins to the Teensy and still have a working SPI flash memory chip on hand.

    But why put the hold and write protect functions into these chips if no one ever uses it?

  3. #178
    Senior Member PaulStoffregen's Avatar
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    Quote Originally Posted by onehorse View Post
    But why put the hold and write protect functions into these chips if no one ever uses it?
    Probably because people within a giant corporation with a lot of clout demanded it. Especially these sorts of features get requested by huge companies with legions of risk-adverse middle managers. They want extra assurance against anticipated problems, and for good reason!

    Many semiconductors are designed around requests from one huge customer. The chip's design gets heavily optimized around then whims of that one customer, who agrees to buy some huge quantity. Then when the public datasheet is written, they pretend it was designed as a general purpose device for everyone.

    Likewise, huge corporations basically fund and staff the standards bodies, like JEDEC. I believe these memory chips, at least up to 128 Mbit size, follow a JEDEC standard. Prior to that standard, other incompatible pinouts and command sets were used (Atmel's old 45 series flash chips, for example). When the features are defined as a standard, it's almost impossible to scrap these sorts of little extras from the standard. Especially when the working committee creating the draft is composed of engineers from half a dozen major companies who want those specific features.

    It's also quite possible some people actually do use those features! I never have, and I've never seen anyone use them, but doesn't mean someone, somewhere isn't. Odds are good a project requirements document for some extremely high volume product wrote usage of those into the spec from the beginning before engineers even worked on the project.

  4. #179
    Senior Member onehorse's Avatar
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    I never have, and I've never seen anyone use them, but doesn't mean someone, somewhere isn't.
    My experience too. But they are there so I made the best of it in the design.

    I ordered the 2 Gbit chips yesterday morning and they are already sitting on my desk!

    How is this even possible?

  5. #180
    Senior Member onehorse's Avatar
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    Looks like Spansion and Cypress have combined to produce NOR Flash. Their latest uses a 65 nm process to give faster rates in the same package. They are offering 512 Mbit flash with a single #CS. I don't want to proliferate a zoo of flash add-ons but being able to offer 0.5, 1, and 2 Gbit in the same form factor is attractive. And I like Spansion over Micron since they have internal pullups on their #WP and #HOLD pins that don't require external resistors. These should work with Paul's library too.

  6. #181
    Senior Member onehorse's Avatar
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    I put together the latest members of the memory board zoo tonight. The Micron N25Q00AA 1 Gbit NOR SPI Flash memory and the MT25QL02G 2 Gbit NOR SPI Flash memory. They both come in a 6 mm x 8 mm BGA-24 package and the board layout is nearly identical except for the silkscreen labeling. They both also have only one #CS so can be used with Paul's SerialFlash library. This is what the 2 Gbit chip produces when running the RawHardwareTest sketch in that library:

    Code:
    Serial enabled!
    Raw SerialFlash Hardware Test
    
    Read Chip Identification:
      JEDEC ID:     20 BA 22
      Part Nummber: (unknown chip)
      Memory Size:  268435456 bytes
      Block Size:   65536 bytes
    
    Reading Chip...
    
    Writing 32 signatures
    
    Double Checking All Signatures:
      all 131072 signatures read ok
    
    Checking Signature Pairs
      all 65535 signature pairs read ok
    
    Checking Read-While-Write (Program Suspend)
      write 256 bytes at 512
      write time was 172 microseconds.
      read-while-writing: 00 00 00 00 15 F5 95 4B 
      test passed, good read while writing
    
    Checking Read-While-Erase (Erase Suspend)
      erase time was 128913 microseconds.
      erase correctly erased 65536 bytes
      read-while-erasing: 00 00 00 00 15 F5 95 4B 
      test passed, good read while erasing
    
    All Tests Passed  :-)
    Here is what it looks like:

    Click image for larger version. 

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    Notice it has 100 K pullups on #WP, #HOLD, and #CS. This still allows quad mode to be used and is necessary because Micron does not add internal pullups like Spansion does.

    These should be for sale on Tindie shortly.
    Last edited by onehorse; 01-27-2016 at 07:11 AM.

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