I have a project coming up that will need subtle changes to the clock of multiple Teensy's in order to synchronize them to a common signal. I know I can do this with parts I'm already using (a dedicated VCXO+PLL part, Pletronics FD77T, sadly discontinued), but I'm wondering if there's just enough functionality in the 3.1's OSC module to manage for prototype purposes. I see OSC_CR has 4 bits of crystal capacitance loading, which is theoretically the means by which a crystal's frequency is adjusted over a small range. The question would be: how big of a range? I don't need an exact frequency match, the PID works for cycle-lock (thus the indivudual units can oscillate frequency back and forth around the control as long as everybody ends up counting the same number of cycles over the medium term), so the mere 16 potential values don't concern me too much except as far as tuning the PID goes.
Any idea if the capacitive "pull" range is anywhere near 2x the crystal's initial tolerance? I'd try it out right now, but I'm deep into a different hardware project and am just getting this question out there while it occurs to me...
Thanks!
Any idea if the capacitive "pull" range is anywhere near 2x the crystal's initial tolerance? I'd try it out right now, but I'm deep into a different hardware project and am just getting this question out there while it occurs to me...
Thanks!