I'm not sure how the read the datasheet (Teensy 3.1) with regard to DMA performance. In this thread, the goal is to have 16 M pin samples per second. I'm not sure if that can be achieved or not, with a Teensy 3.1 running at 96 MHz.
There's a formula given:
Can anyone shed some light on this? How fast can DMA transfer pin samples to SRAM?
Regards
Christoph
There's a formula given:
PEAKreq = freq / [ entry + (1 + read_ws) + (1 + write_ws) + exit ]
where
- freq: System frequency (96 MHz)
- entry: channel startup (4 cycles)
- read_ws: read wait states (2 from peripheral)
- write_ws: write wait states (zero to SRAM)
- exit: channel shutdown (3 cycles)
Can anyone shed some light on this? How fast can DMA transfer pin samples to SRAM?
Regards
Christoph