Teensy very slow I/O write

[steve.pico]

I am currently using an Arduino pro mini and wanted to be have faster I/O write so I am trying a Teensy 3.2. It seemed very slow so I tried this simple test. on my Arduino the output is high for 62.5ns, as expected. On the Teensy 3.2 it is several hundred nsec. Does anyone know why it doesn't write in a single cycle? This is the sole reason for going to the Teensy is to reduce this time to less than 12ns. Is this an IDE compiling issue or does the Teensy take more than 1 cycle to write to I/O?

Any help is appreciated.

*******************

void setup() {
//DDRB=B11111111; }
void loop() {
noInterrupts();
while(1){
PORTB=255;//set all bits high
PORTB=0;//set all bits low - should be high for 1 cycle
}
}

 

[MichaelMeissner]

The Teensy 3.x/LC use ARM processors instead of AVR processors. ARM processors does I/O differently than AVR processors. It provides emulation for the AVR PORT<x> macros, but it would be better to either use the native ARM I/O facility (but you will need to read the 1,000+ page datasheet for details), or use the digitalWriteFast function with constant arguments.

Lets say you were just interested in pin 8. So instead of:

while (1) {
  PORTB |= (1L << (8-8);       // set pin 8 high
  PORTB &= ~(1L << (8-8));    // clear pin 8
}

You would do:

while (1) {
  digitalWriteFast (8, HIGH);
  digitalWriteFast (8, LOW);
}

 

[steve.pico]

Thanks, Michael. I'll try that. Is there a way to write more than one bit to the port at a time, or does this only work for a single pin?

 

[MichaelMeissner]

I'm sure there is a way, but you will have to delve into the ARM specific registers, and it is likely the register numbers that are clumped together will be different than the AVR machines.

 

[steve.pico]

Thank you once again. I'll play with it a bit.

 

[Xenoamor]

I made a thread over here about the topic.

I couldn't get faster than 18MHz.
However I have had 23MHz with 4 staggered DMA channels.

There's no way you'll be able to get 12ns I'm afraid. What do you want that kind of speeds for? You may benefit from looking at CPLDs or FPGAs.

Incase you were still looking GPIOB_PDOR is the ARM equivalent of PORTB
PDOR being Pin Data Output Register (I think). Unlike AVR there's seperate registers for inputs and outputs

 

[Headroom]

If you really do need these speeds the DIPSY project may be just the ticket.

 

[steve.pico]

thanks for the tip, I will have a look at it

 

[steve.pico]

Thanks for the reply. In some cases I'm using my [commercial] device to test data streams and our next generation needs to run at a bit rate of about 100Mbits/second. Most of the time the controller is just managing the UI. The Atmega328 does great, but it's limited to 16Mbits/sec. I can overclock it to maybe 40Mbits/sec, but not sure that is reliable enough for a commercial product. I can also use the Atmega328 to gate SMD clocks, but thought I might be able to get there using the teensy3x. I also thought the teensy3x might have faster rise/fall times and my application is very sensitive to edge jitter. It sounds like I might want to use SMD clocks with the Atmega328, but I'll play some more, since I just got the Teensy board last week.

 

[steve.pico]

Thanks for all of your comments. I did get to 96MB/sec using DigitalWriteFast(). The rise/fall times are a bit slugglish, but it did work and might do just what I need.

 

[PaulStoffregen]

The rise/fall times are a bit slugglish

pinMode() enables the slew rate limiting feature. You can get faster edges if you write to the pin's config register to turn off the slew rate limiting.

 

[steve.pico]

Thanks, Paul. I have a ways to go yet, but having fun

 

[steve.pico]

Paul, I think I already have the fast slew rate selected and I am measuring an edge speed of 1.8ns. That's not terrible, just wondering what the jitter will be. I'll measure that once I have a bit cleaner setup.

Thanks again for the help. One more question and that's whether CE certification is planned for Teensy? It isn't required until 2017, but it would be good to know if RoHs and CE are planned.