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Thread: My Teensy Logic Analyzer

  1. #51
    Senior Member+ KurtE's Avatar
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    Hi,
    I thought I would try installing it again and see how it works...

    Looks like a pretty nice setup for those who do not have hardware Logic Analyzer. Note: first time I tried to run the run.bat, the windows code errored out. Sorry I should have kept the output, but it closed the window and I lost it. Second time it ran...

    I installed the firmware on T3.6, played around a bit to get the GUI to talk to the Teensy.

    From this and now looking at code, I am guessing you need to download a different firmware to the Teensy to get the high speed mode?
    HARDWARE_CONFIGURATION needs to be set to 1.

    Update: Actually looks like you have both sets of firmware and you can have it update the Teensy in the capture dialog which is nice. Note: I tried doing a capture at 120mhz and it looks like it may have hung. Unplugged T3.6, replugged in, tried at 60mhz and it completed. Tried again at 120 and this time went through. Note: I don't have it connected to anything yet. If I downspeed this to 30mhz, I can capture about 34ms, which nice.

    Sorry if below is a little off topic, but will sort of describe what I have been typically doing:

    For me, I am sorry to say I am a bit spoiled as I currently have 3 Analyzers by Saleae (Their earlier 16, a Logic 8, and now a Pro logic 8), I used to have their original Logic, but I gave that one away.

    The reason I recently purchased the Pro, was I wanted to better debug SPI, for example to the ILI9341 display, I found I needed a sample speed near 100mhz, which I could not do on the non-pro for enough IO pins (Miso, Mosi, CLK, CS, DC). And Actually right now I am playing with it connected up to an UP board, where I am actually debugging running one of these display in user mode (SPIDEV using MRAA). Currently trying to see if I can use a hardware CS pin instead of software controlled one. So currently doing: captures of 6 channels at 100mhz for 5 seconds. Note: I can probably run a bit slower than I am as the SPI clock appears to be running at 8.33mhz.

    I also do reasonably long capture time as I am sort of lazy and don't want to worry about setting up triggers, so I can setup to run app on UP board and then start capture and hit enter to start...

    Now back on topic: As defragster mentioned earlier, wonder if it would make sense to build something like Frank's flex board, with memory chips, such that you could increase how long you sample.

    Again I have not very much yet at the code nor at all to the Logic Sniffer code. So I don't know if it was possible and made sense to try to do something similar to what Saleae does and this is when you are doing a capture. Their hardware compresses the data and sending it over the USB port while the capture is happening and that way your limits are dictated more by your USB speed. They use something like RAW HID for this.

    But again great work!

    I will play some more with it some more later. But now back to testing some stuff out on the UP board, plus my parts arrived to build my T3.6 RPI Hat board, which I hope to then plug into UP board... So I have a lot of soldering to do.

  2. #52
    Quote Originally Posted by KurtE View Post
    Hi,
    I thought I would try installing it again and see how it works...
    Thanks for the comments. The next big item to add is compression, which could increase the number of samples by a factor of 10, 100, or more, depending on the data. Still a few months away.

  3. #53
    It took a while, but I finally released update 4.1 to the Logic Analyzer.
    - Adds Run-Length Encoding (compression) to record up to 100 times more samples (10Meg+ on Teensy 3.6).
    - Increases top speed for 8 channels by 67% (80 MHz on Teensy 3.6)
    - 33% more RAM for Teensy 3.5
    - Adds support for Teensy 3.0 (still supports 3.6/3.5/3.2/3.1/LC)
    https://github.com/LAtimes2/TeensyLogicAnalyzer

  4. #54
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    @LAtimes. You TeensyLogicAnalyzer worked like a charm. Took some playing around to get it to capture SPI signals from two T3.5s in a Master-Slave arrangement but got it to work. Here is a screenshot of the captured signals with update 4.1:
    Click image for larger version. 

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    Do you have any suggestions on the settings including how the trigger should get set up for capturing SPI?

    Thanks
    Mike

  5. #55
    Mike,
    Glad that the Logic Analyzer is helping you.

    Quote Originally Posted by mjs513 View Post
    Do you have any suggestions on the settings including how the trigger should get set up for capturing SPI?
    I would recommend that you use the SPI Analyzer mode (Tools -> SPI Analyser ...). It will open a window like this:
    Click image for larger version. 

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    After you have recorded data, set up the signals for the channels you are using and select Analyze. It will then decode the data. It's been a while since I have used it - if you have trouble, I can try it myself Monday.

    Be sure to record using at least twice the clock frequency of the SPI bus. If you are recording with a 3.6, you can use Run Length Encoding up to about 2 MHz SPI bus (record at 5 MHz), and up to about 30 MHz SPI bus with normal recording (80 MHz). Cut these numbers in half for a 3.5. As far as a trigger, trigger on CS going low (Mask checked, Value not checked for the channel number of CS) with a before/after ratio of 1%.

  6. #56
    Senior Member+ defragster's Avatar
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    That has come a long way in 3 years since OP! Nice use of the T_3.6's performance with 80 MHz sampling!

  7. #57
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    @LAtimes. Thanks for your response and suggestion. Just ran it with the parameters you suggested for the trigger and it worked great. Even tried the SPI analyzer - noticed you have several analyzers available - nice. It really is a great tool. Even ran it up to 80Mhz with the T3.6

    Again many thanks
    Mike

  8. #58
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    Don’t forget about the overclock performance boosts

  9. #59
    I can't take credit for the user interface - it's the work of a lot of other people and is common for many processors and FPGAs (see list under Device type pulldown). I just wrote the Teensy back end. Looking forward to porting it to Teensy 4 soon

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