My Teensy Logic Analyzer

Hi,
I thought I would try installing it again and see how it works...

Looks like a pretty nice setup for those who do not have hardware Logic Analyzer. Note: first time I tried to run the run.bat, the windows code errored out. Sorry I should have kept the output, but it closed the window and I lost it. Second time it ran...

I installed the firmware on T3.6, played around a bit to get the GUI to talk to the Teensy.

From this and now looking at code, I am guessing you need to download a different firmware to the Teensy to get the high speed mode?
HARDWARE_CONFIGURATION needs to be set to 1.

Update: Actually looks like you have both sets of firmware and you can have it update the Teensy in the capture dialog which is nice. Note: I tried doing a capture at 120mhz and it looks like it may have hung. Unplugged T3.6, replugged in, tried at 60mhz and it completed. Tried again at 120 and this time went through. Note: I don't have it connected to anything yet. If I downspeed this to 30mhz, I can capture about 34ms, which nice.

Sorry if below is a little off topic, but will sort of describe what I have been typically doing:

For me, I am sorry to say I am a bit spoiled as I currently have 3 Analyzers by Saleae (Their earlier 16, a Logic 8, and now a Pro logic 8), I used to have their original Logic, but I gave that one away.

The reason I recently purchased the Pro, was I wanted to better debug SPI, for example to the ILI9341 display, I found I needed a sample speed near 100mhz, which I could not do on the non-pro for enough IO pins (Miso, Mosi, CLK, CS, DC). And Actually right now I am playing with it connected up to an UP board, where I am actually debugging running one of these display in user mode (SPIDEV using MRAA). Currently trying to see if I can use a hardware CS pin instead of software controlled one. So currently doing: captures of 6 channels at 100mhz for 5 seconds. Note: I can probably run a bit slower than I am as the SPI clock appears to be running at 8.33mhz.

I also do reasonably long capture time as I am sort of lazy and don't want to worry about setting up triggers, so I can setup to run app on UP board and then start capture and hit enter to start...​
Now back on topic: As defragster mentioned earlier, wonder if it would make sense to build something like Frank's flex board, with memory chips, such that you could increase how long you sample.

Again I have not very much yet at the code nor at all to the Logic Sniffer code. So I don't know if it was possible and made sense to try to do something similar to what Saleae does and this is when you are doing a capture. Their hardware compresses the data and sending it over the USB port while the capture is happening and that way your limits are dictated more by your USB speed. They use something like RAW HID for this.

But again great work!

I will play some more with it some more later. But now back to testing some stuff out on the UP board, plus my parts arrived to build my T3.6 RPI Hat board, which I hope to then plug into UP board... So I have a lot of soldering to do.
 
Hi,
I thought I would try installing it again and see how it works...

Thanks for the comments. The next big item to add is compression, which could increase the number of samples by a factor of 10, 100, or more, depending on the data. Still a few months away.
 
It took a while, but I finally released update 4.1 to the Logic Analyzer.
- Adds Run-Length Encoding (compression) to record up to 100 times more samples (10Meg+ on Teensy 3.6).
- Increases top speed for 8 channels by 67% (80 MHz on Teensy 3.6)
- 33% more RAM for Teensy 3.5
- Adds support for Teensy 3.0 (still supports 3.6/3.5/3.2/3.1/LC)
https://github.com/LAtimes2/TeensyLogicAnalyzer
 
@LAtimes. You TeensyLogicAnalyzer worked like a charm. Took some playing around to get it to capture SPI signals from two T3.5s in a Master-Slave arrangement but got it to work. Here is a screenshot of the captured signals with update 4.1:
MasterSlaveTeensySPI.PNG

Do you have any suggestions on the settings including how the trigger should get set up for capturing SPI?

Thanks
Mike
 
Mike,
Glad that the Logic Analyzer is helping you.

Do you have any suggestions on the settings including how the trigger should get set up for capturing SPI?

I would recommend that you use the SPI Analyzer mode (Tools -> SPI Analyser ...). It will open a window like this:
Untitled.png

After you have recorded data, set up the signals for the channels you are using and select Analyze. It will then decode the data. It's been a while since I have used it - if you have trouble, I can try it myself Monday.

Be sure to record using at least twice the clock frequency of the SPI bus. If you are recording with a 3.6, you can use Run Length Encoding up to about 2 MHz SPI bus (record at 5 MHz), and up to about 30 MHz SPI bus with normal recording (80 MHz). Cut these numbers in half for a 3.5. As far as a trigger, trigger on CS going low (Mask checked, Value not checked for the channel number of CS) with a before/after ratio of 1%.
 
@LAtimes. Thanks for your response and suggestion. Just ran it with the parameters you suggested for the trigger and it worked great. Even tried the SPI analyzer - noticed you have several analyzers available - nice. It really is a great tool. Even ran it up to 80Mhz with the T3.6

Again many thanks
Mike
 
I can't take credit for the user interface - it's the work of a lot of other people and is common for many processors and FPGAs (see list under Device type pulldown). I just wrote the Teensy back end. Looking forward to porting it to Teensy 4 soon :cool:
 
Thus looks really interesting, did you ever port to Teensy 4?

I don't see anything yet up on his github project for any progress on the T4, but the readme does show:
(Note: Does not work with Teensy 4 yet. Coming soon)
The comment was added about 2 months ago, so hopefully he has made progress on it!
 
That will be nice! Extra RAM and speed. Including 20X USB device xfer. And some background DMA display updates might even make it real time usable?

screen updates on ili9341 look to be ~53ms apart - with recent code.
 
I recently accidently found this thread. Colour me very impressed.

A current project is to get the "SUMP" VHDL code to work on a cheap Chinese FPGA board (the $15 RV901T). It already has two sets of 32 pin 5V tolerant I/O. There have been some glitches but I think that it is now working with the 0.9.7.2 GUI. I need 32 channels to monitor a 6502 board (16 address + 8 data + 8 misc).

I also tried to roll my own Verilog code for the FPGA, with some partial success, but I found that the (online) documentation of the SUMP protocol in incomplete (for example the meta data command 0x04 is not documented). So it will be useful to look at the Teensy code. I found it impossible to understand where the source code for the GUI was. I was hoping to add some debug, but since I have no idea about java programming it is probably a no go anyway :-( .

So I was very interested to try the Teensy code on spare 3.2. It compiled and downloaded with no issues. It wasn't clear whether I needed the new version of OLS from @LAtimes or whether the original 0.9.7.2 should work. It was also unclear to me what role the config files played. I can see that they define the capabilities, but do they only get used with the 0.9.8-T4.1 version of the OLS GUI?

Anyway I downloaded and used the 0.9.8-T4-1 version and was able to capture some (blank) data. "Show device metadata" also worked.

From the documentation it appears that there is currently a limit of 8 channels/pins. I also have a 3.5 which las a lot of 5V tolerant pins. Is there any reason why the code couldn't be modified to capture on 32 channels? Note: I have only taken a cursery look at the source code. I spotted some assembly code, and will take a closer look, just to get an idea how capture has been implemented.
 
From the documentation it appears that there is currently a limit of 8 channels/pins.

For speed and consistency, it reads an entire input port at once. So it is limited by the number of pins tied to each port. 12 pins is about the max, and I've thought about adding that, but it would be a lot of work for what it adds. The Teensy 4 should have enough speed to read multiple ports and re-arrange the bits - goal is to use have the analyzer channels match the pins on the Teensy.

I also tried to roll my own Verilog code for the FPGA, with some partial success,

I had some success with a Papilio FPGA board, but it wasn't much faster than the 3.5. But it could do 32 channels.

Anyway I downloaded and used the 0.9.8-T4-1 version and was able to capture some (blank) data. "Show device metadata" also worked.

It has a demo mode if you want to see some non-blank data

It wasn't clear whether I needed the new version of OLS from @LAtimes or whether the original 0.9.7.2 should work. It was also unclear to me what role the config files played. I can see that they define the capabilities, but do they only get used with the 0.9.8-T4.1 version of the OLS GUI?

config files have been around forever. I've tried to keep the new OLS GUI backward compatible with older versions. I've also added some additional capabilities to the protocol that the Teensy supports, mostly higher memory amounts, plus flashing the firmware on the board. The config files describe the hardware, so each target needs a unique file for max speed, max channels, amount of memory, and special capabilities. My GUI is the only one with the Teensy config files.

I spotted some assembly code, and will take a closer look, just to get an idea how capture has been implemented.

There are 3 versions of the code, for different speeds. At slower speeds, there is a straightforward version that hopefully allows easier learning of how it works. The high speed version is still in C, but uses lots of tricks to speed things up. The assembly version is for the highest speeds - 8, 5, and 3 cpu clocks per sample, so highly optimized :) . Hopefully I have enough comments to help you understand it.
 
Hi

Would the teensy logic analyzer useful for a new logic analyzer user like me?

Simple stuff : I²C, maybe some SPI and PWM.


I have always some Teensy's (3.2, 3.6) with pins lying around. Maybe an extra T3.5 would be nice for larger max. 5V measurements.
 
Would the teensy logic analyzer be useful for a new logic analyzer user like me?

Yes! Many of us have an extra teensy sitting around. My intent was to make it as easy as possible to set up and run. The instructions are here. It is just a zip/tar file that unpacks to a single directory. If you want to remove it, just delete the directory.

Search the user's guide for Demo mode, which allows learning to use the logic analyzer with built-in signals.
 
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