K66 Beta Test

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From my cheat sheet:
Code: 
7	129	C4	PTD2/LLWU_P13	DISABLED		PTD2/LLWU_P13	SPI0_SOUT	UART2_RX	FTM3_CH2	FB_AD4/SDRAM_A12		I2C0_SCL

FYI - I went through the core_pins.h file and I have found the same pin mapping as you mentioned.
 
Yes, I see there are problems with other pins, too (?) (starting with PIN0 !)
Code: 
95 E10 B10 62 PTB16 DISABLED PTB16 SPI1_SOUT UART0_RX FTM_CLKIN0 FB_AD17 EWM_IN
Edit.. ok..makes sense if UART0 is RX1/TX1

Edit:
But, then.. PIN 3:
Code: 
64 K9 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 RMII0_RXD1/MII0_RXD1 I2C2_SCL I2S0_TXD0 FTM1_QD_
There is I2C_SCL, not SDA.

Edit Pin4, similar problem..

I assume, there is a little bug .) Either in the list, or in the code..
 
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Thanks for pouring over the pin descriptions. I'll edit later this week.

As for the native pins, I can tell you the code on github absolutely does match the hardware. I personally tested all 10 round 1 boards with a hand-wired 42 LED shield and a simple sketch that blinks all 40 pins and the 2 DACs in sequence.

If I seem a little distracted, rest assured it's with a *lot* of relevant stuff. These last couple days I did a quick first attempt at an ethernet shield, using a LAN8720A chip. Submitted it to OSH Park just this morning and ordered all the missing parts from Digikey. While I imagine it'll be a year until we have really good, usable networking, before absolutely finalizing the beta test I want to receive just 1 ethernet packet, even if only a broadcast ARP and ICMP (ping) datagram. There'll be a couple extra boards, if anyone *really* wants to dig into the low-level ethernet stuff.

On shields, a package just arrived today from OSH Park for a 40 LED shield. We're going to start hand soldering these 9 boards tomorrow. Another group with 42 LEDs is coming later...
 
PaulStoffregen said:
first attempt at an ethernet shield... Submitted it to OSH Park just this morning and ordered all the missing parts from Digikey. While I imagine it'll be a year until we have really good, usable networking, before absolutely finalizing the beta test I want to receive just 1 ethernet packet, even if only a broadcast ARP and ICMP (ping) datagram. There'll be a couple extra boards, if anyone *really* wants to dig into the low-level ethernet stuff.
Click to expand...

Well, in an earlier life I did a lot of TCP/UDP/IP testing, so if I can be of assistance ...
 
Interesting Info:

K66:
- The Drive-Strength setting works for PTB0/PTB1, PTC3/PTC4, PTD4-PTD7 only
- Digital Glitch Filter: Port D only

- DMA: 32 Channels

K64:
- The Drive-Strength setting: All pins (??? or "bug" in manual ?)
- Digital Glitch Filter: Port D only

- DMA 16 Channels
 
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I've long thought that it would be wise to build educational boards with a few pins that have extra protection (eg, a resistor and a BAT54S). Then encourage beginners to use these pins.
 
> Can you stick a few solder points on for PTA0/3 (SWD_CLK/SWD_DIO)?

I would also like to see this.
 
Works and blinks faster:)

hehe.. had a well-known-problem.... first attempt...with a usb-charging cable..

@all: you need a usb-MINI cable for the beta-board, not micro.

Edit:

- FastCRC: Works .

- My "Coremark"-sketch with the gcc 4.8 -compiler (192 MHz) (note: integer only):
Code: 
2K performance run parameters for coremark.
CoreMark Size    : 666
Total ticks      : 16824
Total time (secs): 16.824000
Iterations/Sec   : 356.633381
Iterations       : 6000
Compiler version : GCC4.8.4 20140725 (release) [ARM/embedded-4_8-branch revision 213147]
Compiler flags   : 
Memory location  : STACK
seedcrc          : 0xe9f5
[0]crclist       : 0xe714
[0]crcmatrix     : 0x1fd7
[0]crcstate      : 0x8e3a
[0]crcfinal      : 0xa14c
Correct operation validated. See readme.txt for run and reporting rules.
CoreMark 1.0 :[B] 356.633381[/B] / GCC4.8.4 20140725 (release) [ARM/embedded-4_8-branch revision 213147]  / STACK
https://forum.pjrc.com/threads/29017-Cxxmark-Compiler-Performance-LC-3-1?highlight=coremark


 
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Frank B said:
I got my Beta-testboard !
It is luxurious! :)
Click to expand...

Congratulations Frank!
Mine is still 5 miles away where it has been for about 24 hours - at the local post office - after over 200 miles traveling the package needed to rest . . . wait it got done sorting . . . soon . . .
 
Mine should arrive later today as well. Hopefully I will get into town (9 miles away) to pick it up maybe around noon :D
 
ILI9341_t3 library: Works


Edit:

...tried F_BUS overclocking @192 MHz..
SIM_CLKDIV1_OUTDIV2(1) works. 0 not :) (Too fast for the Display or perhaps the the "long" wires, but the Teensy runs happily with SIM_CLKDIV1_OUTDIV2(0) )
 
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Should we coordinate library testing / porting with a list in this thread or via github-issues?
 
So right Frank: I got my Beta-testboard ! It is luxurious!

Did I miss notes on what speeds USB will work at? USB works at 192MHz or any speed tested at 96 or over, except 180MHz? At 180 MHz Win_10 says it saw a bad USB device.

Quite a few times I had to button push to upload? Though now with IDE SerMon online at 192MHz it is working.
Teensy did not respond to a USB-based request to automatically reboot.
Please press the PROGRAM MODE BUTTON on your Teensy to upload your sketch.
Click to expand...
 
Happy Birthday !
180MHz: Maybe there is a trick and the IRC48 clock canbe used somehow.

just for fun, i tried 240 MHz... works.. (but not with SIM_CLKDIV1_OUTDIV4(8); instead value 7 works (?))

Edit:
...but F_BUS with 240MHz does not work :) Oh, there is indeed a limit.. :)
 
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Frank B said:
Happy Birthday !
180MHz: Maybe there is a trick and the IRC48 clock canbe used somehow.

just for fun, i tried 240 MHz... works.. (but not with SIM_CLKDIV1_OUTDIV4(8); instead value 7 works (?))

Edit:
...but F_BUS with 240MHz does not work :) Oh, there is indeed a limit.. :)
Click to expand...

You should slow down before you get a ticket :p
 
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