NXPK66 vs. STM32L4

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Manitou's perf post is a good one - it is nice to see how the MCU's stack up. Would be interesting to see an olde schoole 486 or Pentium-90 reference point. Interesting to see the T_3.1 boosted perf over the T_3.0 so much, and how the T_LC is really in a (ZERO) class between T_3.1 and UNO. Also how the K64 is closer to the T_3.2 than the K66 - perf-wise.

I also backed Kris/onehorse on his KS to support him - but not yet seen a link to his KS posted - Paul's was the first note AFAIK. The link posted above was in answer to a question about Arduino on STM? I've seen it done before where non Teensy users get told where to go - that isn't SPAM.

I ordered a T_3.6 MPU9250 board from Tindie just to see if I could figure out how Kris gets the T_3.6 to run as slow as the low power STM with near the speed of a T_3.2.

Between WFE and yield() in this thread and the ZILCH multitask thread that uses the same or fewer cycles in task switching by replacing the default that eats those cycles in yield() scanning all Serial# ports for serialEvent() calls I've learned some things about Teensy. This thread seems to have had a reason to start - where it went from not being ignored has some value in Teensy usage and perhaps areas to revisit for improved Teensy use cases.

<edit>:Just searched LadyBug - found one each in this thread and the MPU9250 thread - only link is to OSH PCB.

<edit2>: BTW : I also abused the kinetis_hsrun_disable() with my WFE sample and current dropped lower - but then USB comms were spotty as my simple example did it - mostly sleeping at low speed: the only waking interrupt I had was the systick, and time got 2::1 dilated going 240 to 120 MHz. I wondered if duff's Snooze speed mode change dropped the hsrun (by default or with code) - but didn't see an answer. AFAIK If that doesn't auto drop the current will stay higher too - if it auto drops it still needs to be explicitly reset to get over 120 MHz clocking.
 
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At the bottom of this file: https://github.com/manitou48/DUEZoo/blob/master/perf.txt
are some coremark numbers for various MCU's including dragonfly and Teensy
View attachment 9133View attachment 9134

Thanx for posting that Tom.

There is lots of interesting data and conclusions behind that. Both Teensy and STM32L4 use a flash controller that seems to be clocked with 16MHz internally (or the equivalent; correct me if I am wrong there). That in a nutshell means that at a 16Mhz boundary an extra wait state will be added to the flash access. So 72MHz in general is a bad idea as its somewhere in between. But neither Teensy nor STM32L4 show any stair behavior at the 72MHz measurement. Teensy 3.6 has a linear perf curve, as it has a better cache, and hence less FLASH accesses.

Now what is really curious is this power peak @48MHz. In all Teensy controllers ... Is there anything obvious in the architecture of the MCU that causes that ?
 
Flash memory on Teensy 3.x runs at 24 MHz, or a similar frequency if integer division of the core clock isn't 24 MHz. I believe most of the chips are specified for 25 MHz max flash clock. K66 has a slightly higher spec, I believe 28 MHz.

Experimentation has shown the flash memory is the part of the chip least able to overclock.

On Teensy 3.2 and 3.5 the flash is 64 bits wide, for 192 Mbyte/sec with 24 MHz.

On Teensy 3.6 it's 128 bits wide, for 411 Mbyte/sec with 25.7 MHz.
 
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